{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T23:43:58Z","timestamp":1773791038675,"version":"3.50.1"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T00:00:00Z","timestamp":1705881600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T00:00:00Z","timestamp":1705881600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,1,22]]},"DOI":"10.1109\/asp-dac58780.2024.10473788","type":"proceedings-article","created":{"date-parts":[[2024,3,25]],"date-time":"2024-03-25T15:06:53Z","timestamp":1711379213000},"page":"734-739","source":"Crossref","is-referenced-by-count":0,"title":["Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs"],"prefix":"10.1109","author":[{"given":"Alex","family":"Chan","sequence":"first","affiliation":[{"name":"Newcastle University,United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Danil","family":"Sokolov","sequence":"additional","affiliation":[{"name":"Dialog Semiconductor (Renasas),United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Khomenko","sequence":"additional","affiliation":[{"name":"Dialog Semiconductor (Renasas),United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Yakovlev","sequence":"additional","affiliation":[{"name":"Newcastle University,United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/0471224146"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.740016"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1991.139879"},{"key":"ref5","volume-title":"Minimalist homepage","author":"Nowick","year":"1999"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.743711"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FDL56239.2022.9925657"},{"key":"ref8","first-page":"199","article-title":"Signal Graphs: From Self-Timed to Timed Ones","volume-title":"Int. Workshop on Timed Petri Nets","author":"Rosenblum"},{"key":"ref9","volume-title":"Synthesis of Self-Timed VLSI Circuits From Graph-Theoretic Specifications","author":"Chu","year":"1987"},{"key":"ref10","volume-title":"Kommunikation mit automaten (communicating with automata)","author":"Petri","year":"1962"},{"key":"ref11","first-page":"315","article-title":"Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers","volume":"E80-D","author":"Cortadella","year":"1997","journal-title":"IEICE Trans. Information and Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2004.1309112"},{"key":"ref13","first-page":"204","article-title":"A Theory of Asynchronous Circuits","volume-title":"Int. Symp. Theory of Switching","author":"Muller"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660034"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3206732"},{"key":"ref16","volume-title":"Workcraft homepage","year":"2014"},{"key":"ref17","volume-title":"Verification properties","year":"2014"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2011.11"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2018.108"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2019.8667591"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240532"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1999.761530"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.196"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS55711.2022.9970038"},{"key":"ref25","volume-title":"CaSCADE tools","year":"2007"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2907905"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/Andescon.2012.26"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1993.270624"}],"event":{"name":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Incheon, Korea, Republic of","start":{"date-parts":[[2024,1,22]]},"end":{"date-parts":[[2024,1,25]]}},"container-title":["2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10473777\/10473787\/10473788.pdf?arnumber=10473788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:14:56Z","timestamp":1773778496000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10473788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1,22]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/asp-dac58780.2024.10473788","relation":{},"subject":[],"published":{"date-parts":[[2024,1,22]]}}}