{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T13:03:26Z","timestamp":1773320606808,"version":"3.50.1"},"reference-count":40,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003399","name":"Science and Technology Commission of Shanghai Municipality","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003399","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003347","name":"Fudan University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,19]]},"DOI":"10.1109\/asp-dac66049.2026.11420306","type":"proceedings-article","created":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T19:51:15Z","timestamp":1773172275000},"page":"815-821","source":"Crossref","is-referenced-by-count":0,"title":["PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking"],"prefix":"10.1109","author":[{"given":"Hongyang","family":"Pan","sequence":"first","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cunqing","family":"Lan","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiang","family":"Wang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keren","family":"Zhu","sequence":"additional","affiliation":[{"name":"Fudan University,State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics,Shanghai,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.5120\/ijca2021921053"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.14"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2089569"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611836"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.720317"},{"issue":"9","key":"ref7","first-page":"1076","article-title":"Combining technology mapping and placement for delay-minimization in fpga designs","volume":"14","author":"Chen","year":"1995","journal-title":"IEEE TCAD"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CSTIC61820.2024.10531906"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.1999.810630"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277072"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00059"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586230"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3149977"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228442"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00057"},{"key":"ref16","article-title":"EPFL combinational benchmark suite: Epfl logic synthesis benchmarks","year":"2024"},{"key":"ref17","article-title":"Openroad-flow-scripts: Openroad\u2019s scripts implementing an rtl-to-gds flow","year":"2024"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689082"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/264995.264996"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2007.907067"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382637"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-67295-3_4"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.2008.4681558"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920342"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3149977"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323774"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCIAIG.2012.2186810"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323856"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137062"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s10472-011-9258-6"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323999"},{"key":"ref33","first-page":"11051110","article-title":"Openroad: Toward a self-driving, opensource digital layout implementation tool chain","volume-title":"Proc. GOMACTECH","author":"Ajayi"},{"key":"ref34","article-title":"ABC: System for sequential logic synthesis and formal verification","year":"2024"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/43.664231"},{"key":"ref36","article-title":"IWLS 2005 benchmarks","author":"Albrecht","year":"2005"},{"key":"ref37","article-title":"Mockturtle: C++ logic network library","year":"2024"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref39","article-title":"Yosys open synthesis suite","author":"Wolf","year":"2016"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676676"}],"event":{"name":"2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Lantau, Hong Kong","start":{"date-parts":[[2026,1,19]]},"end":{"date-parts":[[2026,1,22]]}},"container-title":["2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11420221\/11420229\/11420306.pdf?arnumber=11420306","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T19:35:51Z","timestamp":1773257751000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11420306\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,19]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/asp-dac66049.2026.11420306","relation":{},"subject":[],"published":{"date-parts":[[2026,1,19]]}}}