{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T21:34:14Z","timestamp":1773264854607,"version":"3.50.1"},"reference-count":34,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,19]]},"DOI":"10.1109\/asp-dac66049.2026.11420420","type":"proceedings-article","created":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T19:51:15Z","timestamp":1773172275000},"page":"282-288","source":"Crossref","is-referenced-by-count":0,"title":["REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models"],"prefix":"10.1109","author":[{"given":"Kyungjun","family":"Min","sequence":"first","affiliation":[{"name":"Pohang University of Science and Technology,Department of Electrical Engineering,Pohang,Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyumin","family":"Cho","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Department of Electrical Engineering,Pohang,Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junhwan","family":"Jang","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Department of Electrical Engineering,Pohang,Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seokhyeong","family":"Kang","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Department of Electrical Engineering,Pohang,Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"40145","article-title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","volume-title":"Proc. ICML","author":"Pei"},{"key":"ref2","first-page":"1","article-title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","author":"Zhong","year":"2023"},{"key":"ref3","first-page":"1","article-title":"ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model","author":"Qin","year":"2025"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323812"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD65511.2025.11189212"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132897"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/dac63849.2025.11133191"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10992789"},{"key":"ref9","first-page":"1","article-title":"Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis","author":"Thorat","year":"2023"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2025.3604320"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676830"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3483089"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657356"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/iclad65226.2025.00020"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10992897"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3643681"},{"key":"ref17","first-page":"1","article-title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair","volume-title":"Proc. ICLR","author":"Liu"},{"key":"ref18","first-page":"1","article-title":"Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design","author":"DeLorenzo","year":"2025"},{"key":"ref19","first-page":"1","article-title":"Improving Large Language Model Hardware Generating Quality through Post-LLM Search","volume-title":"Proc. NeurIPS","author":"Chang"},{"key":"ref20","first-page":"1","article-title":"ComplexVCoder: An LLM-Driven Framework for Systematic Generation of Complex Verilog Code","author":"Zuo","year":"2025"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-06924-6"},{"key":"ref22","first-page":"1","article-title":"AlphaEvolve: A coding agent for scientific and algorithmic discovery","author":"Novikov","year":"2025"},{"key":"ref23","first-page":"32201","article-title":"Evolution of Heuristics: Towards Efficient Automatic Algorithm Design Using Large Language Model","author":"Liu"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.1998.712192"},{"key":"ref25","volume-title":"GPT-4.1-mini"},{"key":"ref26","first-page":"1","article-title":"DeepSeek-V3 Technical Report","volume-title":"DeepSeek-AI","year":"2024"},{"key":"ref27","first-page":"1","article-title":"The Llama 3 Herd of Models","author":"Team","year":"2024"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3718088"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3697118"},{"key":"ref30","volume-title":"Iverilog"},{"key":"ref31","volume-title":"Yosys"},{"key":"ref32","volume-title":"Nangate45 PDK"},{"key":"ref33","volume-title":"REvolution"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v39i1.32007"}],"event":{"name":"2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Lantau, Hong Kong","start":{"date-parts":[[2026,1,19]]},"end":{"date-parts":[[2026,1,22]]}},"container-title":["2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11420221\/11420229\/11420420.pdf?arnumber=11420420","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T05:31:42Z","timestamp":1773207102000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11420420\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,19]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/asp-dac66049.2026.11420420","relation":{},"subject":[],"published":{"date-parts":[[2026,1,19]]}}}