{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T13:03:38Z","timestamp":1773320618438,"version":"3.50.1"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,19]]},"DOI":"10.1109\/asp-dac66049.2026.11420512","type":"proceedings-article","created":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T19:51:15Z","timestamp":1773172275000},"page":"966-972","source":"Crossref","is-referenced-by-count":0,"title":["Standard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors"],"prefix":"10.1109","author":[{"given":"Kairong","family":"Guo","sequence":"first","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haoran","family":"Lu","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Guo","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiarui","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chunyuan","family":"Zhao","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Heng","family":"Wu","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Runsheng","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"Peking University,School of Integrated Circuits,Beijing"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510618"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774720"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM50854.2024.10873524"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1117\/12.2514571"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3220339"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2025.3537955"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10993282"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132817"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2025.3558759"},{"key":"ref10","first-page":"544","article-title":"Layout optimization of CMOS functional cells","volume-title":"24th ACM\/IEEE conference proceedings on Design automation conference - DAC \u201887","author":"Maiasz"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1989.56777"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2014.6820314"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415612"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2962782"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578920"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3632409.3640475"},{"key":"ref17","first-page":"1","article-title":"A routability-driven complimentary-fet (cfet) standard cell synthesis framework using smt","volume-title":"Proceedings of the 39th International Conference on Computer-Aided Design","author":"Cheng"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3065639"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2021.3092769"},{"key":"ref20","first-page":"1","article-title":"Optimal transistor folding and placement for synthesizing standard cells of complementary fet technology","volume-title":"Proceedings of the 61st ACM\/IEEE Design Automation Conference","author":"Kim"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3299902.3309752"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001382"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3037885"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"}],"event":{"name":"2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Lantau, Hong Kong","start":{"date-parts":[[2026,1,19]]},"end":{"date-parts":[[2026,1,22]]}},"container-title":["2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11420221\/11420229\/11420512.pdf?arnumber=11420512","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T19:35:53Z","timestamp":1773257753000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11420512\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,19]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/asp-dac66049.2026.11420512","relation":{},"subject":[],"published":{"date-parts":[[2026,1,19]]}}}