{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:47:55Z","timestamp":1774687675961,"version":"3.50.1"},"reference-count":44,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T00:00:00Z","timestamp":1768780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,19]]},"DOI":"10.1109\/asp-dac66049.2026.11420751","type":"proceedings-article","created":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T19:51:15Z","timestamp":1773172275000},"page":"765-771","source":"Crossref","is-referenced-by-count":2,"title":["C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization"],"prefix":"10.1109","author":[{"given":"Yi-Chen","family":"Lu","sequence":"first","affiliation":[{"name":"NVIDIA Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao-Hsiang","family":"Hsiao","sequence":"additional","affiliation":[{"name":"NVIDIA Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rongjian","family":"Liang","sequence":"additional","affiliation":[{"name":"NVIDIA Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen-Hao","family":"Liu","sequence":"additional","affiliation":[{"name":"NVIDIA Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haoxing","family":"Ren","sequence":"additional","affiliation":[{"name":"NVIDIA Research"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578926"},{"key":"ref2","article-title":"Iwls 2005 benchmarks","volume-title":"International Workshop for Logic Synthesis (IWLS)","volume":"9","author":"Albrecht"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003843"},{"key":"ref5","article-title":"Pytorch: An imperative style, high-performance deep learning library","author":"Paszke","year":"2019","journal-title":"Advances in neural information processing systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774725"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633313"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1145\/3676536.3676803","article-title":"Hybrid modeling and weighting for timing-driven placement with efficient calibration","volume-title":"Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design","author":"Fu"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530486"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132858"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10993273"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473959"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3698364.3705342"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247660"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3636461"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3572993"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364463"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.crma.2012.03.014"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1145\/3489517.3530485","article-title":"Xplace: An extremely fast and extensible global placement framework","volume-title":"Proceedings of the 59th ACM\/IEEE Design Automation Conference","author":"Liu"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633318"},{"key":"ref21","first-page":"275","article-title":"Progress and challenges in vlsi placement research","volume-title":"Proceedings of the International Conference on Computer-Aided Design","author":"Markov"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3346291"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372666"},{"key":"ref25","article-title":"Primetime user guide: Advanced timing analysis","year":"2023","journal-title":"V-2023.03, Synopsys online Documentation"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578923"},{"key":"ref28","volume-title":"Vlsi placement optimization using graph neural networks","author":"Lu"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586138"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11132448"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10248008"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218582"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3698364.3705353"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3139310"},{"key":"ref35","first-page":"1","article-title":"Ml-based physical design parameter optimization for 3d ics: From parameter selection to optimization","volume-title":"Proceedings of the 61st ACM\/IEEE Design Automation Conference","author":"Hsiao"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD55463.2022.9900103"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD66269.2025.11240744"},{"key":"ref38","first-page":"1","article-title":"A fast learning-driven signoff power optimization framework. In 2020 IEEE","volume-title":"ACM International Conference On Computer Aided Design (ICCAD)","author":"Lu"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643435"},{"key":"ref40","doi-asserted-by":"crossref","DOI":"10.1109\/ASP-DAC66049.2026.11420682","article-title":"Differentiable tier assignment for timing and congestion-aware routing in 3 d ics","volume-title":"2026 31st ACM\/IEEE Asia South Pacific Design Automation Conference (ASP-DAC)","author":"Lu"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3447045"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633328"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-99872-0_14"},{"key":"ref44","article-title":"Accelerating gate sizing using gpu","volume-title":"European Conference on Parallel Processing","author":"Chung"}],"event":{"name":"2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Lantau, Hong Kong","start":{"date-parts":[[2026,1,19]]},"end":{"date-parts":[[2026,1,22]]}},"container-title":["2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11420221\/11420229\/11420751.pdf?arnumber=11420751","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T05:17:39Z","timestamp":1773206259000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11420751\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,19]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/asp-dac66049.2026.11420751","relation":{},"subject":[],"published":{"date-parts":[[2026,1,19]]}}}