{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:52:08Z","timestamp":1730199128151,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/aspdac.2006.1594693","type":"proceedings-article","created":{"date-parts":[[2006,3,22]],"date-time":"2006-03-22T12:38:08Z","timestamp":1143031088000},"page":"266-272","source":"Crossref","is-referenced-by-count":0,"title":["A transduction-based framework to synthesize RSFQ circuits"],"prefix":"10.1109","author":[{"given":"S.","family":"Yamashita","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Tanaka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Takada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Obata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Takagi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/77.783700"},{"key":"15","article-title":"Logic synthesis and optimization benchmarks user guide version 3.0","author":"yang","year":"1991","journal-title":"MCNC"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/77.919539"},{"key":"13","article-title":"SIS: A system for sequential circuit synthesis","volume":"ucb erl m92 41","author":"sentovich","year":"1992","journal-title":"Technical Report"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/43.856972"},{"key":"11","first-page":"353","author":"sawada","year":"1995","journal-title":"Logic Synthesis for Look-up Table Based FPGAs Using Functional Decomposition and Support Minimization"},{"key":"12","first-page":"41","article-title":"Implementation of oversampling analog-to-digital converter based on RSFQ logic","volume":"1","author":"semenov","year":"1997","journal-title":"Extend Abstracts of ISEC 97"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/77.622205"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"journal-title":"Technical Report","year":"2004","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114954"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/77.80745"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/77.919334"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/77.783914"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-8440-3_11"},{"key":"9","first-page":"202","article-title":"Design method of dual-rail RSFQ logic circuits using 2\ufffd2-join","volume":"j88 c","author":"obata","year":"2005","journal-title":"IEICE Trans"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/12.35836"}],"event":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","location":"Yokohama, Japan"},"container-title":["Asia and South Pacific Conference on Design Automation, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10626\/33561\/01594693.pdf?arnumber=1594693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T14:56:33Z","timestamp":1489503393000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1594693\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2006.1594693","relation":{},"subject":[]}}