{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:13:29Z","timestamp":1729617209524,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/aspdac.2006.1594703","type":"proceedings-article","created":{"date-parts":[[2006,3,22]],"date-time":"2006-03-22T17:38:08Z","timestamp":1143049088000},"page":"326-331","source":"Crossref","is-referenced-by-count":0,"title":["Spec-based flip-flop and latch repeater planning"],"prefix":"10.1109","author":[{"family":"Man Chung Hon","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"crossref","first-page":"526","DOI":"10.1090\/qam\/253822","article-title":"An algorithm for finding shortest routes from all source nodes to a given destination in general networks","volume":"27","author":"yen","year":"1970","journal-title":"Quarterly of Applied Mathematics"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120788"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(97)00002-3"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774609"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.819422"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240906"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382587"},{"key":"7","first-page":"215","article-title":"Retiming for wire pipelining in system-on-chip","author":"lin","year":"2003","journal-title":"Proceedings of the 2003 International Conference on on Computer-aided Design"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1016\/0196-6774(88)90008-9"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/256292.256301"},{"key":"9","doi-asserted-by":"crossref","first-page":"451","DOI":"10.1109\/TCAD.2004.825841","article-title":"Repeater scaling and its impact on cad","volume":"23","author":"saxena","year":"2004","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"key":"8","first-page":"690","article-title":"Flip-flop and repeater insertion for early interconnect planning","author":"lu","year":"2002","journal-title":"Proceedings of the conference on Design Automation and Test in Europe"}],"event":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","location":"Yokohama, Japan"},"container-title":["Asia and South Pacific Conference on Design Automation, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10626\/33561\/01594703.pdf?arnumber=1594703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,17]],"date-time":"2019-04-17T13:31:20Z","timestamp":1555507880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1594703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2006.1594703","relation":{},"subject":[]}}