{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:03:27Z","timestamp":1725393807359},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/aspdac.2006.1594729","type":"proceedings-article","created":{"date-parts":[[2006,3,22]],"date-time":"2006-03-22T12:38:08Z","timestamp":1143031088000},"page":"466-472","source":"Crossref","is-referenced-by-count":1,"title":["A fast logic simulator using a look up table cascade emulator"],"prefix":"10.1109","author":[{"given":"H.","family":"Nakahara","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Sasao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Matsuura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"15"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/ICCAD.1994.629776"},{"year":"0","key":"13"},{"year":"0","key":"14"},{"key":"11","first-page":"415","article-title":"Logic synthesis for a single large look-up table","author":"hirose","year":"1995","journal-title":"ICCD1995"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/ICCAD.1995.480147"},{"key":"3","first-page":"225","article-title":"A cascade realization of multiple-output function for reconfigurable hardware","author":"sasao","year":"2001","journal-title":"IWLS-2001"},{"key":"2","first-page":"63","article-title":"LUT cascades and emulators for realizations of logic functions","author":"sasao","year":"2005","journal-title":"RM2005"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/9780470544389"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/TC.1986.1676819"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/ICCAD.1993.580029"},{"key":"6","first-page":"431","article-title":"Optimization methods in look-up table rings","author":"sasao","year":"2004","journal-title":"IWLS 2004"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/ICCAD.1995.480148"},{"key":"4","first-page":"428","article-title":"A method to decompose multiple-output logic functions","author":"sasao","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"9","first-page":"52","article-title":"Shared binary decision diagram with attributed edges for efficient boolean function manipulation","author":"minato","year":"1991","journal-title":"Proc Design Automation Conference"},{"year":"1991","author":"yang","journal-title":"Logic Synthesis and Optimization Benchmark User Guide Version 3 0","key":"8"}],"event":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","location":"Yokohama, Japan"},"container-title":["Asia and South Pacific Conference on Design Automation, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10626\/33561\/01594729.pdf?arnumber=1594729","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T14:31:42Z","timestamp":1489501902000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1594729\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2006.1594729","relation":{},"subject":[]}}