{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,25]],"date-time":"2025-07-25T10:14:39Z","timestamp":1753438479876,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/aspdac.2006.1594783","type":"proceedings-article","created":{"date-parts":[[2006,3,22]],"date-time":"2006-03-22T17:38:08Z","timestamp":1143049088000},"page":"796-801","source":"Crossref","is-referenced-by-count":18,"title":["Finding optimal L1 cache configuration for embedded systems"],"prefix":"10.1109","author":[{"given":"A.","family":"Janapsatya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Ignjatovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Parameswaran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"17","article-title":"Cacti 3.0: An integrated cache timing, power, and area model","volume":"2001","author":"shivakumar","year":"2001","journal-title":"Technical Report"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332663"},{"key":"15","article-title":"MediaBench: A tool for evaluating multimedia and communications systems","author":"lee","year":"1997","journal-title":"IEEE Micro 20"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/WSC.1990.129605"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253681"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006227"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/PADS.1995.404304"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1145\/996566.996652","article-title":"High level cache simulation for heterogeneous multiprocessors","author":"pieper","year":"2004","journal-title":"DAC"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998259"},{"key":"2","first-page":"1703","article-title":"A 160MHz, 32b, 0.5W CMOS RISC microprocessor","volume":"31","author":"montanaro","year":"1996","journal-title":"JSSC"},{"journal-title":"Xtensa Processor","year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/200912.200918"},{"journal-title":"Dinero IV Trace-Driven Uniprocessor Cache Simulator","year":"0","author":"edler","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/973097.973099"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/325478.325479"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/371636.371752"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/12.40842"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"}],"event":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","location":"Yokohama, Japan"},"container-title":["Asia and South Pacific Conference on Design Automation, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10626\/33561\/01594783.pdf?arnumber=1594783","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,3]],"date-time":"2024-02-03T12:19:12Z","timestamp":1706962752000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1594783\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2006.1594783","relation":{},"subject":[]}}