{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T14:41:53Z","timestamp":1725633713677},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,1]]},"DOI":"10.1109\/aspdac.2008.4483926","type":"proceedings-article","created":{"date-parts":[[2008,4,10]],"date-time":"2008-04-10T14:56:31Z","timestamp":1207839391000},"page":"131-137","source":"Crossref","is-referenced-by-count":1,"title":["Timing-power optimization for mixed-radix Ling adders by integer linear programming"],"prefix":"10.1109","author":[{"family":"Yi Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jianhua Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Haikun Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chung-Kuan Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","first-page":"123","article-title":"non-heuristic optimization and synthesis of parallel prefix adders","author":"zimmermann","year":"1996","journal-title":"Proc of In Workshop on Logic and Architecture Synthesis"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1117\/12.472935"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121061"},{"key":"11","first-page":"362","article-title":"a subnanosecond 0.5 m 64b adder design","author":"naffziger","year":"1996","journal-title":"Int Solid State Circuits Conf"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219822"},{"year":"0","key":"3"},{"year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675982"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810056"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"6","first-page":"269","article-title":"logical effort of carry progapate adders","author":"harris","year":"2004","journal-title":"IEEE Intnl Conf on Application-specific Systems Architectures and Processors"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2004.1399375"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.26"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358053"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1147\/rd.252.0156"}],"event":{"name":"2008 Asia and South Pacific Design Automation Conference (ASPDAC)","start":{"date-parts":[[2008,3,21]]},"location":"Seoul, South Korea","end":{"date-parts":[[2008,3,24]]}},"container-title":["2008 Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4480121\/4483913\/04483926.pdf?arnumber=4483926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T11:29:48Z","timestamp":1489663788000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4483926\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2008.4483926","relation":{},"subject":[],"published":{"date-parts":[[2008,1]]}}}