{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:09:00Z","timestamp":1729616940799,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/aspdac.2009.4796556","type":"proceedings-article","created":{"date-parts":[[2009,3,5]],"date-time":"2009-03-05T19:53:27Z","timestamp":1236282807000},"page":"666-671","source":"Crossref","is-referenced-by-count":1,"title":["Conflict driven scan chain configuration for high transition fault coverage and low test power"],"prefix":"10.1109","author":[{"family":"Zhen Chen","sequence":"first","affiliation":[]},{"family":"Boxue Yin","sequence":"additional","affiliation":[]},{"given":"Dong","family":"Xiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/43.238615"},{"key":"22","article-title":"low- capture-power test generation for scan-based at-speed testing","author":"wen","year":"2005","journal-title":"Proc of IEEE Int Test Conference"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527892"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1002"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/92.311647"},{"key":"24","article-title":"pattern-directed circuit virtual partitioning for test power reduction","author":"xu","year":"2007","journal-title":"Proc of IEEE Int Test Conference"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.85"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966682"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527893"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805824"},{"key":"11","first-page":"438","article-title":"on structural vs. functional testing for delay faults","author":"krstic","year":"2003","journal-title":"Proc ofISQED"},{"key":"12","doi-asserted-by":"crossref","first-page":"638","DOI":"10.1109\/43.277638","article-title":"reducing correlation to improve coverage of delay faults in scan-path design","volume":"13","author":"mao","year":"1994","journal-title":"IEEE Trans on Computer-Aided Design"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.55"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.807890"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269074"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"1","first-page":"187","article-title":"improving transi- tion delay fault coverage using hybrid scan-based tech- nique","author":"amhed","year":"2005","journal-title":"Proc of 20th IEEE Int Symp on Defect and Fault-Tolerance in VLSI Systems"},{"key":"10","first-page":"175","article-title":"constrained atpg for broadside transition testing","author":"liu andm","year":"2003","journal-title":"Proc of IEEE Int Symp on De- fect and Fault-Tolerance in VLSI Systems"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2006.313252"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583983"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FTCSH.1995.532648"},{"key":"4","doi-asserted-by":"crossref","first-page":"1971","DOI":"10.1109\/43.251160","article-title":"transition fault testing for sequen- tial circuits","volume":"12","author":"cheng","year":"1993","journal-title":"IEEE Trans on Computer-Aided Design"},{"key":"9","doi-asserted-by":"crossref","first-page":"1535","DOI":"10.1109\/TCAD.2005.857379","article-title":"pseudofunctional testing","volume":"25","author":"lin","year":"2006","journal-title":"IEEE Trans on Computer-Aided Design"},{"key":"8","article-title":"a framework of high-quality transition fault atpg for scan circuits","author":"kajihara","year":"2006","journal-title":"Proc of IEEE Int Test Conference"}],"event":{"name":"2009 Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2009,1,19]]},"location":"Yokohama, Japan","end":{"date-parts":[[2009,1,22]]}},"container-title":["2009 Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4781528\/4796414\/04796556.pdf?arnumber=4796556","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T10:52:38Z","timestamp":1602672758000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4796556"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2009.4796556","relation":{},"subject":[],"published":{"date-parts":[[2009,1]]}}}