{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:09:08Z","timestamp":1767262148219},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/aspdac.2010.5419690","type":"proceedings-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T14:36:49Z","timestamp":1267540609000},"page":"825-831","source":"Crossref","is-referenced-by-count":58,"title":["Slack redistribution for graceful degradation under voltage overscaling"],"prefix":"10.1109","author":[{"given":"Andrew B.","family":"Kahng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seokhyeong","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Sartori","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"327","article-title":"Selective gate-length biasing for cost-effective runtime leakage control","author":"gupta","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857313"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1996.507753"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313834"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810282"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416652"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393383"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref18","article-title":"Testing the Critical Operating Point (COP) Hypothesis using FPGA Emulation of Timing Errors in Over-Scaled Soft-Processors","author":"narayanan","year":"2009","journal-title":"IEEE Workshop on Silicon Errors in Logic"},{"key":"ref19","article-title":"CMOS Process Variations: A Critical Operation Point Hypothesis","author":"patel","year":"2008","journal-title":"Online Presentation"},{"journal-title":"Cadence SignalStorm User's Manual","year":"0","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566437"},{"journal-title":"Synopsys Prime'Iime User's Manual","year":"0","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243978"},{"key":"ref6","first-page":"326","article-title":"Tilos: A Polynomial Programming Approach to Transistor Sizing","author":"fishburn","year":"1985","journal-title":"proc ACM\/IEEE International Conference on Computer-Aided Design"},{"journal-title":"Cadence SOCEncounter User's Manual","year":"0","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798256"},{"key":"ref7","article-title":"CRISTA: A new paradigm for low-power and robust circuit synthesis under parameter variations using critical path isolation","author":"ghosh","year":"2007","journal-title":"TCAD"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.13"},{"key":"ref1","first-page":"2","article-title":"Oppotunities and Challenges for Better Than Worst-Case Design","author":"austin","year":"2005","journal-title":"Proc Asia and South Pacific Design Automation Conf"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771810"},{"journal-title":"OpenSPARC T1 Architectural Transplants","year":"0","author":"chung","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/92.994980"},{"journal-title":"International technology roadmap for semiconductors 2008 update","year":"0","key":"ref24"},{"journal-title":"Microproceesors White Papers","article-title":"Enhanced Intel Speed Step Technology for the Intel Pentium M Processor","year":"2004","key":"ref23"},{"journal-title":"Synopsys Design Compiler User's Manual","year":"0","key":"ref26"},{"journal-title":"Sun OpenSPARC Project","year":"0","key":"ref25"}],"event":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010)","start":{"date-parts":[[2010,1,18]]},"location":"Taipei","end":{"date-parts":[[2010,1,21]]}},"container-title":["2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5415928\/5419673\/05419690.pdf?arnumber=5419690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T11:41:24Z","timestamp":1602675684000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5419690"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2010.5419690","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}