{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:05:44Z","timestamp":1759147544059},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/aspdac.2010.5419807","type":"proceedings-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:36:49Z","timestamp":1267558609000},"page":"637-644","source":"Crossref","is-referenced-by-count":37,"title":["A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography"],"prefix":"10.1109","author":[{"given":"Jae-Seok","family":"Yang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Katrina","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minsik","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun","family":"Yuan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology","author":"yang","year":"2008","journal-title":"Proc Int Conf on Computer Aided Design"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1117\/12.814299","article-title":"Design-Overlay Interactions in Metal Double Patterning","author":"ghaida","year":"2009","journal-title":"Proc SPIE 7275"},{"key":"ref12","article-title":"Variability aware interconnect timing models for double patterning","author":"chin","year":"2009","journal-title":"Proc SPIE 7275"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1117\/12.772891","article-title":"Post-decomposition assessment of double patterning layout","author":"rubinstein","year":"2008","journal-title":"Proc SPIE 6924"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1109\/ICCAD.2000.896453","article-title":"Miller Factor for Gate-Level Coupling Delay Calculation","author":"chen","year":"2000","journal-title":"Proc Int Conf on Computer Aided Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2000.855281"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1117\/12.773107","article-title":"Development of layout split algorithms and printability evaluation for double patterning technology","author":"chiou","year":"2008","journal-title":"Proc SPIE 6924"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351308"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681616"},{"key":"ref5","article-title":"Double Patterning Technology Friendly Detailed Routing","author":"cho","year":"2008","journal-title":"Proc Int Conf on Computer Aided Design"},{"key":"ref8","article-title":"A Linear-Time Heuristic for Improving Network Partitions","author":"fiduccia","year":"1982","journal-title":"Proc Design Automation Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514958"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1117\/12.712773","article-title":"Double pattern EDA solutions for 32nm HP and beyond","author":"bailey","year":"2007","journal-title":"Proc SPIE 6521"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1117\/12.773575","article-title":"Sources of Overlay Error in Double Patterning Integration Schemes","author":"laidler","year":"2008","journal-title":"Proc SPIE 6922"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1117\/3.401208"}],"event":{"name":"2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010","start":{"date-parts":[[2010,1,18]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2010,1,21]]}},"container-title":["2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5415928\/5419673\/05419807.pdf?arnumber=5419807","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:47:03Z","timestamp":1602690423000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5419807"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2010.5419807","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}