{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:08:45Z","timestamp":1742378925849,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/aspdac.2010.5419834","type":"proceedings-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:36:49Z","timestamp":1267558609000},"page":"493-498","source":"Crossref","is-referenced-by-count":27,"title":["Improved weight assignment for logic switching activity during at-speed test pattern generation"],"prefix":"10.1109","author":[{"given":"M.-F.","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-C.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.-H.","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.-L.","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Kun-Han Tsai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Wu-Tung Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775860"},{"key":"ref11","article-title":"Power-aware test: Challenges and solutions","author":"ravi","year":"2007","journal-title":"Proc International Test Conference"},{"key":"ref12","first-page":"526","article-title":"Methodology for low power test pattern generation using activity threshold control logic","author":"ravi","year":"2007","journal-title":"Proc Int Conf on Computer-Aided Design"},{"key":"ref13","first-page":"32.2.1","article-title":"Preferred fill: A scalable method to reduce capture power for scan based designs","author":"remersaro","year":"2006","journal-title":"Proc International Test Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358089"},{"key":"ref17","first-page":"25.1.1","article-title":"A novel scheme to reduce power supply noise for high-quality at-speed scan testing","author":"wen","year":"2007","journal-title":"Proc International Test Conference"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.13"},{"key":"ref19","first-page":"13.1.1","article-title":"Reducing power supply noise in linear-decompressor-based test data compression environment for at-speed scan testing","author":"wu","year":"2008","journal-title":"Proc International Test Conference"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.34"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700585"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003802"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437596"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1109\/ISVLSI.2005.53","article-title":"On reducing peak current and power during test","author":"li","year":"2005","journal-title":"IEEE Proc Computer Society Annual Symp VLSI"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1172","DOI":"10.1145\/1403375.1403661","article-title":"Layout-aware, ir-drop tolerant transition fault pattern generation","author":"lee","year":"2008","journal-title":"Proc Design Automation and Test in Europe Conference"},{"key":"ref2","first-page":"533","article-title":"Transition delay fault test pattern generation considering supply voltage noise in a soc design","author":"ahmed","year":"2007","journal-title":"Proc Design Automation Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.77"},{"key":"ref9","article-title":"High-frequency, at-speed scan testing","volume":"20","author":"lin","year":"2003","journal-title":"IEEE Design and Test of Computers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560093"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"}],"event":{"name":"2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010","start":{"date-parts":[[2010,1,18]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2010,1,21]]}},"container-title":["2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5415928\/5419673\/05419834.pdf?arnumber=5419834","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:47:10Z","timestamp":1602690430000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5419834"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2010.5419834","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}