{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:03:32Z","timestamp":1725555812201},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/aspdac.2010.5419842","type":"proceedings-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T19:36:49Z","timestamp":1267558609000},"page":"444-449","source":"Crossref","is-referenced-by-count":0,"title":["Combined use of rising and falling edge triggered clocks for peak current reduction in IP-Based SoC designs"],"prefix":"10.1109","author":[{"family":"Tsung-Yi Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tzi-Wei Kao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Shi-Yi Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tai-Lun Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"How-Rern Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/0-306-48139-1_16"},{"journal-title":"Specification for the Wishbone System-On-Chip (SoC) Interconnection Architecture for Portable IP Cores","year":"2002","key":"ref11"},{"year":"2001","key":"ref12"},{"journal-title":"AMBA Specification","year":"1999","key":"ref13"},{"year":"0","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357983"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.402499"},{"year":"0","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996772"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e91-a.12.3803"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065629"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547520"},{"key":"ref8","first-page":"376","article-title":"Skew aware polarity assignment in clock tree","author":"chen","year":"2007","journal-title":"Proc of ICCAD"},{"key":"ref7","first-page":"558","article-title":"Clock buffer polarity assignment for power noise reduction","author":"samanta","year":"2006","journal-title":"Proc of ICCAD"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.848085"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194706"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124725"}],"event":{"name":"2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010","start":{"date-parts":[[2010,1,18]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2010,1,21]]}},"container-title":["2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5415928\/5419673\/05419842.pdf?arnumber=5419842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:47:19Z","timestamp":1602690439000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5419842"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2010.5419842","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}