{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:20:25Z","timestamp":1729624825404,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/aspdac.2010.5419914","type":"proceedings-article","created":{"date-parts":[[2010,3,2]],"date-time":"2010-03-02T14:36:49Z","timestamp":1267540609000},"page":"95-100","source":"Crossref","is-referenced-by-count":2,"title":["Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory"],"prefix":"10.1109","author":[{"family":"Yi He","sequence":"first","affiliation":[]},{"family":"Chun Jason Xue","sequence":"additional","affiliation":[]},{"family":"Cathy Qun Xu","sequence":"additional","affiliation":[]},{"given":"Edwin H.-M.","family":"Sha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74939"},{"key":"ref11","first-page":"212","article-title":"Optimizing page replacement for multiple-level memory hierarchy","volume":"6","author":"sha","year":"1999","journal-title":"International Journal of Computers and Their Applications"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1145\/1176760.1176809","article-title":"Integrated scratchpad memory optimization and task scheduling for mpsoc architectures","author":"suhendra","year":"2006","journal-title":"CASES '06 Proceedings of the 2006 international conference on Compilers architecture and synthesis for embedded systems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289824"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054944"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1998.666245"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450144"},{"key":"ref5","first-page":"224","article-title":"Reducing off-chip memory access costs using data recomputation in embedded chip multi-processors","author":"koc","year":"2007","journal-title":"Proceedings of the 44th Annual Conference on Design Automation-DAC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011119519789"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2004.1363044"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/581888.581891"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/321623.321632"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2006.66"}],"event":{"name":"2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010","start":{"date-parts":[[2010,1,18]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2010,1,21]]}},"container-title":["2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5415928\/5419673\/05419914.pdf?arnumber=5419914","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T01:44:14Z","timestamp":1497836654000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5419914\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2010.5419914","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}