{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T12:50:40Z","timestamp":1744203040328,"version":"3.28.0"},"reference-count":45,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/aspdac.2011.5722184","type":"proceedings-article","created":{"date-parts":[[2011,3,5]],"date-time":"2011-03-05T12:54:28Z","timestamp":1299329668000},"page":"197-203","source":"Crossref","is-referenced-by-count":19,"title":["Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC"],"prefix":"10.1109","author":[{"given":"Meng-Fan","family":"Chang","sequence":"first","affiliation":[]},{"given":"Pi-Feng","family":"Chiu","sequence":"additional","affiliation":[]},{"given":"Shyh-Shyuan","family":"Sheu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"510","article-title":"A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure","author":"park","year":"0","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2002.1014915"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884079"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034414"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873215"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852159"},{"key":"ref37","first-page":"265","article-title":"Highly area efficient and cost effective double stacked S^3 (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM","author":"jung","year":"2004","journal-title":"Proc Int Electron Devices Meeting (IEDM)"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"284","DOI":"10.1109\/ISSCC.2003.1234303","article-title":"512Mb PROM with 8 layers of antifuse\/diode cells","volume":"1","author":"crowley","year":"0","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC) Dig Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915429"},{"key":"ref34","first-page":"165","article-title":"Three-dimensional shared memory fabricated using wafer stacking technology","author":"lee","year":"2000","journal-title":"Proc Int Electron Devices Meeting (IEDM)"},{"key":"ref10","first-page":"332","article-title":"A sub-200mV 6T SRAM in 0.13?m CMOS","author":"zhai","year":"0","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC) Dig Tech Papers"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/NVSMW.2008.30"},{"key":"ref11","first-page":"2592","article-title":"A 256kb subthreshold SRAM in 65nm CMOS","author":"calhoun","year":"0","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.873640"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859016"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"},{"key":"ref15","first-page":"474","article-title":"A 512kB embedded Phase Change Memory with 416kB\/s write through at 100uA cell write current","author":"hanzawa","year":"2007","journal-title":"ISSCC"},{"key":"ref16","first-page":"268","article-title":"A 90nm 4Mb embedded Phase-Change memory with 1.2V 12ns read access time and IMB\/s write throughput","author":"sandre","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556227"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.909751"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040120"},{"key":"ref28","first-page":"82","article-title":"A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme","author":"sheu","year":"2009","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2006794"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796677"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.862343"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433914"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref5","first-page":"423","article-title":"Robust ultralow voltage ROM design","author":"seok","year":"2008","journal-title":"IEEE CICC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1999.797248"},{"journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)","article-title":"Ultra-low-voltage circuit design forum","year":"0","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013763"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560286"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892207"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810048"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/4.910492"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419228"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2023192"},{"key":"ref23","article-title":"Time discrete voltage sensing and iterative programming control for a 4F2 multilevel CBRAM","author":"schrogmeier","year":"2007","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346730"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346733"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/.2006.1629510"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609461"}],"event":{"name":"2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011","start":{"date-parts":[[2011,1,25]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,1,28]]}},"container-title":["16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5716646\/5722157\/05722184.pdf?arnumber=5722184","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T20:31:47Z","timestamp":1497904307000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5722184\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":45,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2011.5722184","relation":{},"subject":[],"published":{"date-parts":[[2011,1]]}}}