{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,29]],"date-time":"2025-08-29T10:10:27Z","timestamp":1756462227899},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/aspdac.2011.5722210","type":"proceedings-article","created":{"date-parts":[[2011,3,5]],"date-time":"2011-03-05T12:54:28Z","timestamp":1299329668000},"page":"336-343","source":"Crossref","is-referenced-by-count":41,"title":["CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits"],"prefix":"10.1109","author":[{"given":"Shashikanth","family":"Bobba","sequence":"first","affiliation":[]},{"given":"Ashutosh","family":"Chakraborty","sequence":"additional","affiliation":[]},{"given":"Olivier","family":"Thomas","sequence":"additional","affiliation":[]},{"given":"Perrine","family":"Batude","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Ernst","sequence":"additional","affiliation":[]},{"given":"Olivier","family":"Faynot","sequence":"additional","affiliation":[]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"ref11","first-page":"166","article-title":"GeOI and SOI 3-D monolithic cell integrations for high density applications","author":"batude","year":"2009","journal-title":"Proc VLSI Tech"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424352"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358084"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.3.2"},{"key":"ref15","article-title":"CASCADE: A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-heavy very Large Scale Integrated Circuits","author":"zhou","year":"2006","journal-title":"IEEE Trans CAD"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1194993"},{"year":"0","key":"ref17"},{"year":"0","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123056"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796761"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/5.929646"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388565"},{"key":"ref6","first-page":"82","article-title":"High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W\/L Scheme for Standalone and Embedded Memory","author":"jung","year":"2007","journal-title":"Proc VLSI Tech"},{"year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123055"},{"year":"0","key":"ref7"},{"journal-title":"Three-Dimensional Integrated Circuit Design","year":"2009","author":"pavlidis","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055187"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630029"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/785411.785414"},{"year":"0","key":"ref24","article-title":"Nangate 45nm Library"},{"year":"0","key":"ref23","article-title":"Gurobi Optimization"},{"year":"0","key":"ref26","article-title":"SOC Encounter tool"},{"year":"0","key":"ref25","article-title":"Synopsys Design Compiler"}],"event":{"name":"2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011","start":{"date-parts":[[2011,1,25]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,1,28]]}},"container-title":["16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5716646\/5722157\/05722210.pdf?arnumber=5722210","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:50:52Z","timestamp":1490079052000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5722210\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2011.5722210","relation":{},"subject":[],"published":{"date-parts":[[2011,1]]}}}