{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:38:44Z","timestamp":1729651124248,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/aspdac.2011.5722220","type":"proceedings-article","created":{"date-parts":[[2011,3,5]],"date-time":"2011-03-05T07:54:28Z","timestamp":1299311668000},"page":"395-401","source":"Crossref","is-referenced-by-count":0,"title":["All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era"],"prefix":"10.1109","author":[{"given":"Soichi","family":"Inoue","sequence":"first","affiliation":[]},{"given":"Sachiko","family":"Kobayashi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Design intention application to tolerance-based manufacturing system","author":"kobayashi","year":"2010","journal-title":"Proc SPIE 7641 76410L"},{"key":"ref3","article-title":"Manufacturing system based on tolerance deduced from design intention","author":"kyoh","year":"2009","journal-title":"Proc SPIE 7275 72750M"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1117\/12.710299"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.594834"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1117\/12.793031"},{"key":"ref5","article-title":"Utilization of Design Intent Information for Mask Manufacturing","author":"kato","year":"2008","journal-title":"Photomask Technology Proc SPIE 7028&#x2013;109"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1117\/12.772747","article-title":"Systematic yield estimation method with lithography simulation","volume":"6925?25","author":"kyoh","year":"2008","journal-title":"Proc SPIE"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1117\/12.656858","article-title":"Lithography oriented DfM for 65nm and beyond","volume":"6156?14","author":"kyoh","year":"2006","journal-title":"Proc SPIE"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1117\/12.657806","article-title":"Development of hot spot fixer","volume":"6156?51","author":"kotani","year":"2006","journal-title":"Proc SPIE"},{"key":"ref2","first-page":"91","article-title":"Patterning Friendly Design Methodology for 65-nm and Beyond Technology Nodes","author":"inoue","year":"2005","journal-title":"Proceedings of IFST 2005"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1117\/12.681852"},{"key":"ref1","article-title":"Total hot spot management from design rule definition to silicon fabrication","author":"inoue","year":"2003","journal-title":"Electronic Design Processes Workshop EDP"}],"event":{"name":"2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011","start":{"date-parts":[[2011,1,25]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,1,28]]}},"container-title":["16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5716646\/5722157\/05722220.pdf?arnumber=5722220","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T16:31:43Z","timestamp":1497889903000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5722220\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2011.5722220","relation":{},"subject":[],"published":{"date-parts":[[2011,1]]}}}