{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:57:44Z","timestamp":1729659464386,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/aspdac.2011.5722237","type":"proceedings-article","created":{"date-parts":[[2011,3,5]],"date-time":"2011-03-05T07:54:28Z","timestamp":1299311668000},"page":"479-484","source":"Crossref","is-referenced-by-count":3,"title":["Managing complexity in design debugging with sequential abstraction and refinement"],"prefix":"10.1109","author":[{"given":"Brian","family":"Keng","sequence":"first","affiliation":[]},{"given":"Andreas","family":"Veneris","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2009.5351130"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419816"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366131"},{"key":"ref13","first-page":"33","article-title":"Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis","author":"chauhan","year":"2002","journal-title":"Formal Methods in CAD"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1007\/3-540-36577-X_2","article-title":"Automatic abstraction without counterex-amples","author":"mcmillan","year":"2003","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829807"},{"year":"2007","key":"ref16"},{"key":"ref17","first-page":"75","article-title":"PicoSAT essentials","volume":"4","author":"biere","year":"2008","journal-title":"JSAT"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1007\/978-3-540-70545-1_3","article-title":"Assertion-based verification: Industry myths to realities (invited tutorial)","author":"foster","year":"2008","journal-title":"Computer Aided Verification"},{"key":"ref3","first-page":"1045","article-title":"Sunulation-based bug trace minimization with BMC-based refinement","author":"chang","year":"2005","journal-title":"ICCAD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013998"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852031"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1803","DOI":"10.1109\/43.811329","article-title":"Design error diagnosis and correction Via test vector simulation","volume":"18","author":"venens","year":"1999","journal-title":"IEEE Trans on CAD"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5693-0","author":"huang","year":"1998","journal-title":"Format Equivalence Checking and Design Debugging"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/11560548_20"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0302-6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030593"}],"event":{"name":"2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011","start":{"date-parts":[[2011,1,25]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,1,28]]}},"container-title":["16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5716646\/5722157\/05722237.pdf?arnumber=5722237","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,8]],"date-time":"2019-06-08T21:14:09Z","timestamp":1560028449000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5722237\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2011.5722237","relation":{},"subject":[],"published":{"date-parts":[[2011,1]]}}}