{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T06:19:43Z","timestamp":1725776383097},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/aspdac.2011.5722303","type":"proceedings-article","created":{"date-parts":[[2011,3,5]],"date-time":"2011-03-05T12:54:28Z","timestamp":1299329668000},"page":"818-823","source":"Crossref","is-referenced-by-count":8,"title":["Secure scan design using shift register equivalents against differential behavior attack"],"prefix":"10.1109","author":[{"given":"Hideo","family":"Fujiwara","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Katsuya","family":"Fujiwara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideo","family":"Tamamoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.89"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.15"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.20"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.906483"},{"key":"ref14","first-page":"413","article-title":"Secure and testable scan design using extended de Brujin graph","author":"fujiwara","year":"0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491786"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270887"},{"year":"0","key":"ref17"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1109\/OLT.2004.1319691","article-title":"Scan design and secure chip","author":"hely","year":"2004","journal-title":"10th IEEE International On-Line Testing Symposium"},{"key":"ref3","first-page":"6","article-title":"Design and test of an integrated cryptochip","author":"hafner","year":"1999","journal-title":"IEEE Design and Test of Computers"},{"key":"ref6","first-page":"339","article-title":"Scan based side channel attack on dedicated hardware implementations of data encryptionstandard","author":"yang","year":"0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5000-z"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862745"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4317.001.0001","author":"fujiwara","year":"1985","journal-title":"Logic Testing and Design for Testability"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224313"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70215"}],"event":{"name":"2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011","start":{"date-parts":[[2011,1,25]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,1,28]]}},"container-title":["16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5716646\/5722157\/05722303.pdf?arnumber=5722303","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,9]],"date-time":"2019-06-09T01:13:59Z","timestamp":1560042839000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5722303\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2011.5722303","relation":{},"subject":[],"published":{"date-parts":[[2011,1]]}}}