{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:05:30Z","timestamp":1747868730819,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/aspdac.2012.6164964","type":"proceedings-article","created":{"date-parts":[[2012,3,13]],"date-time":"2012-03-13T16:53:37Z","timestamp":1331657617000},"page":"304-309","source":"Crossref","is-referenced-by-count":8,"title":["Optimizing test-generation to the execution platform"],"prefix":"10.1109","author":[{"given":"Amir","family":"Nahir","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avi","family":"Ziv","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subrat","family":"Panda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/43.898827"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0541"},{"key":"15","first-page":"146","article-title":"Advances in simultaneous multithreading testcase generation methods","volume":"6504","author":"adir","year":"2010","journal-title":"LNCS"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"13","article-title":"Constraint-based random stimuli generation for hardware verification","author":"naveh","year":"2006","journal-title":"AAAI"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996578"},{"journal-title":"Random Test Generators for Microprocessor Design Validation","year":"2006","author":"storm","key":"11"},{"key":"12","first-page":"60","article-title":"Reaching coverage closure in post-silicon validation","volume":"6504","author":"adir","year":"2010","journal-title":"LNCS"},{"journal-title":"Model checking","year":"1999","author":"clarke","key":"3"},{"journal-title":"Comprehensive Functional Verification The Complete Industry Cycle","year":"2005","author":"wile","key":"2"},{"journal-title":"International Technology Roadmap for Semiconductors 2009 Edition - Design","year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763252"},{"key":"7","first-page":"99","article-title":"Automatic functional test program generation for pipelined processors using model checking","author":"mishra","year":"0","journal-title":"Seventh Annual IEEE International Workshop on High-Level Design Validation and Test October 2002"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319972"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1147\/sj.413.0386"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884494"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2117370"}],"event":{"name":"2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2012,1,30]]},"location":"Sydney, Australia","end":{"date-parts":[[2012,2,2]]}},"container-title":["17th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6156603\/6164924\/06164964.pdf?arnumber=6164964","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:05:37Z","timestamp":1490101537000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6164964\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2012.6164964","relation":{},"subject":[],"published":{"date-parts":[[2012,1]]}}}