{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T00:02:38Z","timestamp":1725753758967},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/aspdac.2012.6165057","type":"proceedings-article","created":{"date-parts":[[2012,3,13]],"date-time":"2012-03-13T16:53:37Z","timestamp":1331657617000},"page":"763-768","source":"Crossref","is-referenced-by-count":3,"title":["Selective time borrowing for DSP pipelines with hybrid voltage control loop"],"prefix":"10.1109","author":[{"given":"Paul N.","family":"Whatmough","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shidhartha","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David M.","family":"Bull","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Izzat","family":"Darwazeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"667","article-title":"Soft-edge flip-flops for improved timing yield: Design and optimization","author":"joshi","year":"2007","journal-title":"IEEE\/ACM Int Conf on Computer-Aided Design"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSSE.1998.738077"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024946"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079410"},{"journal-title":"VLSI Digital Signal Processing Systems Design and Implementation","year":"1999","author":"parhi","key":"10"},{"journal-title":"Discrete-Time Signal Processing","year":"2009","author":"oppenheim","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537581"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821775"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009135"},{"journal-title":"Computer Arithmetic Algorithms and Hardware Designs","year":"2010","author":"parhami","key":"9"},{"journal-title":"Binary Adder Architectures for Cell-Based VLSI and Their Synthesis","year":"1998","author":"zimmermann","key":"8"}],"event":{"name":"2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2012,1,30]]},"location":"Sydney, Australia","end":{"date-parts":[[2012,2,2]]}},"container-title":["17th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6156603\/6164924\/06165057.pdf?arnumber=6165057","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:09:16Z","timestamp":1490101756000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6165057\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2012.6165057","relation":{},"subject":[],"published":{"date-parts":[[2012,1]]}}}