{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T08:38:19Z","timestamp":1725698299820},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/aspdac.2012.6165059","type":"proceedings-article","created":{"date-parts":[[2012,3,13]],"date-time":"2012-03-13T16:53:37Z","timestamp":1331657617000},"page":"775-780","source":"Crossref","is-referenced-by-count":7,"title":["BTI-aware design using variable latency units"],"prefix":"10.1109","author":[{"given":"Saket","family":"Gupta","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"56","article-title":"Mapping for better than worst-case delays in LUT-based FPGA designs","author":"cong","year":"2008","journal-title":"Proc Int l Symp Field-Programmable Gate Arrays"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"11"},{"journal-title":"Predictive Technology Model","year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896305"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/12.795120"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.03.019"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.910130"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"6","first-page":"195","article-title":"Variable-latency adder (VLadder): New arithmetic circuit design practice to overcome NBTI","author":"chen","year":"2007","journal-title":"Proceedings of the international symposium on Low power electronics and design"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466113"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2058874"},{"key":"9","first-page":"493","article-title":"An analytical model for negative bias temperature instability","author":"kumar","year":"2006","journal-title":"Proceedings of the International Conference on Computer-Aided Design"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2036628"}],"event":{"name":"2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2012,1,30]]},"location":"Sydney, Australia","end":{"date-parts":[[2012,2,2]]}},"container-title":["17th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6156603\/6164924\/06165059.pdf?arnumber=6165059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:12:43Z","timestamp":1490101963000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6165059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2012.6165059","relation":{},"subject":[],"published":{"date-parts":[[2012,1]]}}}