{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:10:18Z","timestamp":1729624218345,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1109\/aspdac.2013.6509630","type":"proceedings-article","created":{"date-parts":[[2013,5,3]],"date-time":"2013-05-03T23:36:53Z","timestamp":1367624213000},"page":"403-410","source":"Crossref","is-referenced-by-count":6,"title":["Design issues in heterogeneous 3D\/2.5D integration"],"prefix":"10.1109","author":[{"given":"D.","family":"Milojevic","sequence":"first","affiliation":[]},{"given":"P.","family":"Marchal","sequence":"additional","affiliation":[]},{"given":"E. J.","family":"Marinissen","sequence":"additional","affiliation":[]},{"given":"G.","family":"Van der Plas","sequence":"additional","affiliation":[]},{"given":"D.","family":"Verkest","sequence":"additional","affiliation":[]},{"given":"E.","family":"Beyne","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"Ieee standard test access port and boundary-scan architecture","author":"society","year":"2001","journal-title":"IEEE Std 1149 1TM-2001"},{"key":"22","doi-asserted-by":"crossref","DOI":"10.1007\/0-387-34609-0","volume":"35","author":"da silva","year":"2006","journal-title":"The Core Test Wrapper Handbook Rationale and Application of IEEE Std 1500?"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.58"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139180"},{"key":"18","first-page":"4","article-title":"DfT architecture and atpg for interconnect tests of jedec wide-i\/o memory-on-logic die stacks","volume":"12","author":"sa","year":"2012","journal-title":"Proceedings IEEE International Test Conference (ITC)"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5269-9"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751450"},{"key":"13","article-title":"An analytical compact model for estimation of stress in multiple through-silicon via configurations","author":"eneman","year":"2010","journal-title":"Proc DATE 2011"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469556"},{"key":"11","first-page":"1","author":"laudon","year":"2006","journal-title":"UltraSPARC T1 A 32-threaded CMP for Servers"},{"journal-title":"Active Heat Sinks","year":"2012","key":"12"},{"key":"21","article-title":"Ieee standard testability method for embedded core-based integrated circuits","author":"society","year":"2001","journal-title":"IEEE Std 1500TM-2005"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0367-5"},{"key":"2","first-page":"1","article-title":"Cost-driven 3d integration with interconnect layers","author":"xie","year":"2010","journal-title":"Quality Electronic Design 2006 ISQED'06 7th International Symposium on"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"year":"0","key":"10"},{"key":"7","article-title":"8Gb 3D DDR3 DRAM using through-silicon-via technology","author":"kang","year":"2009","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2009.5416563"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055357"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"year":"0","key":"8"}],"event":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013)","start":{"date-parts":[[2013,1,22]]},"location":"Yokohama","end":{"date-parts":[[2013,1,25]]}},"container-title":["2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6507004\/6509548\/06509630.pdf?arnumber=6509630","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T12:31:17Z","timestamp":1498048277000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6509630\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2013.6509630","relation":{},"subject":[],"published":{"date-parts":[[2013,1]]}}}