{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:00:32Z","timestamp":1729627232152,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/aspdac.2014.6742865","type":"proceedings-article","created":{"date-parts":[[2014,2,21]],"date-time":"2014-02-21T16:20:31Z","timestamp":1392999631000},"page":"47-52","source":"Crossref","is-referenced-by-count":2,"title":["Lithographic defect aware placement using compact standard Cells without inter-cell margin"],"prefix":"10.1109","author":[{"given":"Seongbo","family":"Shim","sequence":"first","affiliation":[]},{"given":"Yoojong","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"786","article-title":"Reducing DfM to practice: The lithography manufacturability assessor","author":"liebmann","year":"2006","journal-title":"Proc SPIE"},{"key":"2","first-page":"128","article-title":"Yield enhancement with DFM","author":"paek","year":"2012","journal-title":"Proc SPIE"},{"year":"0","key":"10"},{"key":"1","first-page":"8684031","article-title":"Litho-friendly design (LfD) methodologies applied to library cells","author":"peter","year":"2013","journal-title":"Proc SPIE"},{"key":"7","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatric","year":"1983","journal-title":"Science"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1145\/1231996.1232004"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1117\/3.401208"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1117\/12.2015173"},{"key":"9","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1117\/12.534538","article-title":"Standard cell design with regularly placed contacts and gates","volume":"5379","author":"wang","year":"2004","journal-title":"Proc SPIE"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/JSSC.1985.1052337"},{"year":"2005","author":"andres","journal-title":"Integrated circuit layout design methodology with process variation bands","key":"11"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/LPE.2004.1349331"}],"event":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2014,1,20]]},"location":"Singapore","end":{"date-parts":[[2014,1,23]]}},"container-title":["2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6736726\/6742831\/06742865.pdf?arnumber=6742865","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T04:21:07Z","timestamp":1498105267000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6742865\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2014.6742865","relation":{},"subject":[],"published":{"date-parts":[[2014,1]]}}}