{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:47:43Z","timestamp":1774687663481,"version":"3.50.1"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/aspdac.2014.6742866","type":"proceedings-article","created":{"date-parts":[[2014,2,21]],"date-time":"2014-02-21T21:20:31Z","timestamp":1393017631000},"page":"53-60","source":"Crossref","is-referenced-by-count":9,"title":["Structural planning of 3D-IC interconnects by block alignment"],"prefix":"10.1109","author":[{"given":"Johann","family":"Knechtel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Evangeline F. Y.","family":"Young","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Lienig","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870076"},{"key":"17","first-page":"6222","article-title":"VLSI block placement with alignment constraints based on corner block list","volume":"6","author":"chen","year":"2005","journal-title":"Proc Int Symp Circuits Syst"},{"key":"18","author":"knechtel","year":"2013","journal-title":"Corblivar Floorplanning Suite"},{"key":"15","first-page":"8","article-title":"Corner block list: An effective and efficient topological representation of non-slicing floorplan","author":"hong","year":"2000","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973076"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228495"},{"key":"14","author":"lim","year":"2013","journal-title":"Folded 2-die Block"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509679"},{"key":"12","first-page":"1","article-title":"A new architecture for power network in 3D IC","author":"chen","year":"2011","journal-title":"Proc Des Autom Test Europe"},{"key":"21","author":"coskun","year":"2011","journal-title":"Hotspot 3D Extension"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1115\/InterPACK2009-89072"},{"key":"22","first-page":"590","article-title":"3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits","author":"zhou","year":"2007","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"23","author":"chen","year":"2010","journal-title":"3DFP - Thermal-aware floorplanner for three-dimensional ICs"},{"key":"24","author":"ng","year":"0"},{"key":"25","year":"2000","journal-title":"GSRC Benchmark"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.09.003"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"3","first-page":"66","article-title":"Bus-driven floorplanning","author":"xiang","year":"2003","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"2","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1145\/1150019.1136497","article-title":"Design and management of 3D chip multiprocessors using network-in-memory","author":"li","year":"2006","journal-title":"Proc Int Symp Comput Archit"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429538"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2065990"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796505"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127994"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055247"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2007.09.002"},{"key":"9","first-page":"335","article-title":"Block-level 3D IC design with throughsilicon-via planning","author":"kim","year":"2012","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2174640"}],"event":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Singapore","start":{"date-parts":[[2014,1,20]]},"end":{"date-parts":[[2014,1,23]]}},"container-title":["2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6736726\/6742831\/06742866.pdf?arnumber=6742866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T08:21:01Z","timestamp":1498119661000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6742866\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2014.6742866","relation":{},"subject":[],"published":{"date-parts":[[2014,1]]}}}