{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,6]],"date-time":"2025-10-06T09:16:38Z","timestamp":1759742198538},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/aspdac.2014.6742992","type":"proceedings-article","created":{"date-parts":[[2014,2,21]],"date-time":"2014-02-21T16:20:31Z","timestamp":1392999631000},"page":"825-830","source":"Crossref","is-referenced-by-count":19,"title":["Modeling and design analysis of 3D vertical resistive memory &amp;#x2014; A low cost cross-point architecture"],"prefix":"10.1109","author":[{"given":"Cong","family":"Xu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"IC Cost Model Revision 1202a","year":"0","key":"17"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2009.935695"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479018"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333712"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2136443"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177078"},{"key":"2","first-page":"260","article-title":"A 0.13 um 64Mb multi-layered conductive metaloxide memory","author":"chevallier","year":"2010","journal-title":"Proceedings of the IEEE Solid-state Circuits Conference Digest of Technical Papers (ISSCC)"},{"key":"1","article-title":"Bit cost scalable (BiCS) technology for future ultra high density storage memories","author":"nitayama","year":"2013","journal-title":"Proc IEEE VLSI Tech Symp"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941484"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479083"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131654"},{"key":"4","first-page":"432","article-title":"A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology","author":"liu","year":"2013","journal-title":"IEEE International Solid-State Circuits Conference"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1063\/1.3693392"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/2422094.2422103"}],"event":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2014,1,20]]},"location":"Singapore","end":{"date-parts":[[2014,1,23]]}},"container-title":["2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6736726\/6742831\/06742992.pdf?arnumber=6742992","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T19:16:43Z","timestamp":1490296603000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6742992\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2014.6742992","relation":{},"subject":[],"published":{"date-parts":[[2014,1]]}}}