{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:17:34Z","timestamp":1763457454451,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/aspdac.2015.7058985","type":"proceedings-article","created":{"date-parts":[[2015,3,13]],"date-time":"2015-03-13T21:06:37Z","timestamp":1426280797000},"page":"81-86","source":"Crossref","is-referenced-by-count":18,"title":["Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI"],"prefix":"10.1109","author":[{"given":"Adam","family":"Teman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Meinerzhagen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Burg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548579"},{"key":"ref3","article-title":"A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme","author":"kim","year":"2007","journal-title":"IEEE ISSCC 2007"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164009"},{"key":"ref5","article-title":"Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology","volume":"1","author":"meinerzhagen","year":"2011","journal-title":"IEEE JETCAS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2358699"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref9","article-title":"A 1.1 GHz 12 uA\/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications","volume":"43","author":"wang","year":"2008","journal-title":"IEEE JSSC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649106"}],"event":{"name":"2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2015,1,19]]},"location":"Chiba, Japan","end":{"date-parts":[[2015,1,22]]}},"container-title":["The 20th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7050531\/7058915\/07058985.pdf?arnumber=7058985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T18:13:21Z","timestamp":1490379201000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7058985\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2015.7058985","relation":{},"subject":[],"published":{"date-parts":[[2015,1]]}}}