{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T10:24:56Z","timestamp":1725618296436},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/aspdac.2015.7059044","type":"proceedings-article","created":{"date-parts":[[2015,3,13]],"date-time":"2015-03-13T17:06:37Z","timestamp":1426266397000},"page":"429-434","source":"Crossref","is-referenced-by-count":5,"title":["Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories"],"prefix":"10.1109","author":[{"given":"Guantao","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tim","family":"Schmidt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rainer","family":"Domer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ajit","family":"Dingankar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Desmond","family":"Kirkpatrick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Thread affinity mapping for irregular data access on shared Cache GPGPU","author":"kuo","year":"2012","journal-title":"Design Automation Conference (ASP-DAC) 2012 17th Asia and South Pacific"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/5.747869"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1272366.1272380"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391628"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTR.2009.5289173"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.197"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1111\/j.1749-6632.1980.tb29690.x"},{"journal-title":"Intel&#x00AE; Xeon Phi&#x2122; Coprocssor High-Performance Programming","year":"2013","author":"jeffers","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"journal-title":"Tilera Multicore Processors","year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657025"},{"journal-title":"Intel Xeon Phi Coprocessors System Software Developers Guide","year":"2013","key":"ref2"},{"journal-title":"Intel Xeon Phi Coprocessor Datasheet","year":"2013","key":"ref1"},{"key":"ref9","article-title":"A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs","author":"lai","year":"2014","journal-title":"IEEE Transactions on Computers"}],"event":{"name":"2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2015,1,19]]},"location":"Chiba, Japan","end":{"date-parts":[[2015,1,22]]}},"container-title":["The 20th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7050531\/7058915\/07059044.pdf?arnumber=7059044","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T14:33:43Z","timestamp":1490366023000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7059044\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2015.7059044","relation":{},"subject":[],"published":{"date-parts":[[2015,1]]}}}