{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:48:27Z","timestamp":1730198907106,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/aspdac.2015.7059047","type":"proceedings-article","created":{"date-parts":[[2015,3,13]],"date-time":"2015-03-13T17:06:37Z","timestamp":1426266397000},"page":"447-453","source":"Crossref","is-referenced-by-count":2,"title":["Physical verification flow for hierarchical analog ic design constraints"],"prefix":"10.1109","author":[{"given":"Volker","family":"Meyer zu Bexten","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Tristl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Goran","family":"Jerke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hartmut","family":"Marquardt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dina","family":"Medhat","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Mentor Graphics Corp","year":"2014","key":"ref10"},{"journal-title":"Synopsys Inc","year":"2014","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2012.6232874"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.1998.715450"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.259949"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.881335"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"article-title":"User-Controlled Layout Synthesis for Analog Integrated Circuits","year":"1994","author":"meyer zu bexten","key":"ref4"},{"article-title":"A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits","year":"1996","author":"chang","key":"ref3"},{"article-title":"Analog Layout Synthesis: A Survey of Topo-logical Approaches","year":"2010","author":"graeb","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450415"},{"key":"ref8","article-title":"A Logic-Driven Layout Verification System for Multi-Domain Design Analysis","author":"pikus","year":"2010","journal-title":"Proc IEEE Int Workshop on Design for Manuf & Yield"},{"key":"ref7","first-page":"271","article-title":"Constraint-Driven Design Methodology: A Path to Analong Design Automation","volume":"6","author":"jerke","year":"2010"},{"year":"2013","key":"ref2","article-title":"Road vehicles - Functional safety"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2013","key":"ref1"},{"journal-title":"Cadence Design Systems Inc","year":"2014","key":"ref9"}],"event":{"name":"2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2015,1,19]]},"location":"Chiba, Japan","end":{"date-parts":[[2015,1,22]]}},"container-title":["The 20th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7050531\/7058915\/07059047.pdf?arnumber=7059047","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T23:57:28Z","timestamp":1490313448000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7059047\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2015.7059047","relation":{},"subject":[],"published":{"date-parts":[[2015,1]]}}}