{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:01:59Z","timestamp":1781884919899,"version":"3.54.5"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/aspdac.2015.7059059","type":"proceedings-article","created":{"date-parts":[[2015,3,13]],"date-time":"2015-03-13T17:06:37Z","timestamp":1426266397000},"page":"520-525","source":"Crossref","is-referenced-by-count":6,"title":["An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST"],"prefix":"10.1109","author":[{"family":"Liang-Che Li","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Wen-Hsuan Hsu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Kuen-Jong Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Chun-Lung Hsu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-31494-0_8"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699219"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"737","DOI":"10.1109\/TCAD.2012.2236837","article-title":"Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis","volume":"32","author":"lin","year":"2013","journal-title":"IEEE Trans Comput -Aided Des Integrated Circuits & Syst"},{"key":"ref6","first-page":"1","article-title":"Post-bond test techniques for TSVs with crosstalk faults in 3D ICs","author":"huang","year":"2012","journal-title":"Proc Int Symp VLSI Design Automat Test (VLSI-DAT)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810665"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783749"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2011.5985896"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.22"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1621","DOI":"10.1109\/TVLSI.2011.2160410","article-title":"Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint","volume":"20","author":"xu","year":"2012","journal-title":"IEEE Trans on VLSI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-012-5322-3"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007458"}],"event":{"name":"2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Chiba, Japan","start":{"date-parts":[[2015,1,19]]},"end":{"date-parts":[[2015,1,22]]}},"container-title":["The 20th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7050531\/7058915\/07059059.pdf?arnumber=7059059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:20:01Z","timestamp":1498188001000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7059059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2015.7059059","relation":{},"subject":[],"published":{"date-parts":[[2015,1]]}}}