{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:12:46Z","timestamp":1725534766577},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/aspdac.2016.7427972","type":"proceedings-article","created":{"date-parts":[[2016,3,10]],"date-time":"2016-03-10T16:48:08Z","timestamp":1457628488000},"page":"1-2","source":"Crossref","is-referenced-by-count":2,"title":["An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection"],"prefix":"10.1109","author":[{"given":"Dongsheng","family":"Yang","sequence":"first","affiliation":[]},{"given":"Wei","family":"Deng","sequence":"additional","affiliation":[]},{"given":"Aravind Tharayil","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Kengo","family":"Nakata","sequence":"additional","affiliation":[]},{"given":"Teerachot","family":"Siriburanon","sequence":"additional","affiliation":[]},{"given":"Kenichi","family":"Okada","sequence":"additional","affiliation":[]},{"given":"Akira","family":"Matsuzawa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"360","article-title":"A 1.7GHz MDLL-based fractional-N frequency synthesizer with l.4ps RMS integrated jitter and 3mW power using a 1b TDC","author":"marucci","year":"2014","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230543"},{"key":"ref6","first-page":"1","article-title":"A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique","author":"deng","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"336","article-title":"An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS","author":"pyoungwon","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055347"},{"key":"ref1","first-page":"266","article-title":"A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique","author":"deng","year":"2014","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2016,1,25]]},"location":"Macao, Macao","end":{"date-parts":[[2016,1,28]]}},"container-title":["2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7422345\/7427971\/7427972.pdf?arnumber=7427972","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T21:32:11Z","timestamp":1475184731000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7427972\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2016.7427972","relation":{},"subject":[],"published":{"date-parts":[[2016,1]]}}}