{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T18:40:26Z","timestamp":1780339226361,"version":"3.54.1"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/aspdac.2016.7427997","type":"proceedings-article","created":{"date-parts":[[2016,3,10]],"date-time":"2016-03-10T21:48:08Z","timestamp":1457646488000},"page":"109-114","source":"Crossref","is-referenced-by-count":39,"title":["Architecture design with STT-RAM: Opportunities and challenges"],"prefix":"10.1109","author":[{"given":"Ping","family":"Chi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shuangchen","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yuanqing Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yu Lu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seung H.","family":"Kang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"ti34","article-title":"Novel highly scalable multi-level cell for STT-MRAM with stacked perpendicular MTJs","author":"aoki","year":"2013","journal-title":"2013 VLSIT"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1880037.1880040"},{"key":"ref12","first-page":"50","article-title":"Relaxing nonvolatility for fast and energy-efficient STT-RAM caches","author":"smullen","year":"2011","journal-title":"HPCA'll"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483060"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"ref15","first-page":"610","article-title":"A coherent hybrid SRAM and STT-RAM Ll cache architecture for shared memory multicores","author":"wang","year":"2014","journal-title":"ASP-DAC '14"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001367"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744908"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835947"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333705"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555758"},{"key":"ref8","first-page":"1","article-title":"7.5 A 3.3ns-access-time 71.2\/-LW\/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"ISSCC'15"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.2324563"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPSA.2012.050990"},{"key":"ref9","first-page":"224","article-title":"Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology","author":"yu","year":"2013","journal-title":"ISSCC'13"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105304"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228447"},{"key":"ref23","first-page":"216","article-title":"Energy-efficient spin-transfer torque RAM cache exploiting additional all-zero-data flags","author":"jung","year":"2013","journal-title":"ISQED&#x2019;13"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.179"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840931"}],"event":{"name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Macao, Macao","start":{"date-parts":[[2016,1,25]]},"end":{"date-parts":[[2016,1,28]]}},"container-title":["2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7422345\/7427971\/7427997.pdf?arnumber=7427997","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,30]],"date-time":"2016-09-30T01:32:32Z","timestamp":1475199152000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7427997\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2016.7427997","relation":{},"subject":[],"published":{"date-parts":[[2016,1]]}}}