{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:48:44Z","timestamp":1730198924339,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/aspdac.2017.7858313","type":"proceedings-article","created":{"date-parts":[[2017,2,20]],"date-time":"2017-02-20T16:36:54Z","timestamp":1487608614000},"page":"157-162","source":"Crossref","is-referenced-by-count":3,"title":["Multi-level logic benchmarks: An exactness study"],"prefix":"10.1109","author":[{"given":"Luca","family":"Amaru","sequence":"first","affiliation":[]},{"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[]},{"given":"Winston","family":"Haaswijk","sequence":"additional","affiliation":[]},{"given":"Eleonora","family":"Testa","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Vuillod","sequence":"additional","affiliation":[]},{"given":"Jiong","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"ref10","article-title":"Exact benchmarks section"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887922"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/BF02579196"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808597"},{"article-title":"Synthesis and optimization of digital circuits","year":"1994","author":"de micheli","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643371"},{"key":"ref16","article-title":"Faster logic manipulation for large designs","author":"mishchenko","year":"2013","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref17","article-title":"SAT-based Functional Dependency Computation","author":"soeken","year":"2016","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"year":"0","key":"ref19","article-title":"ABC synthesis tool-available"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.858726"},{"key":"ref3","article-title":"The EPFL Combinational Benchmark Suite","author":"amaru","year":"2015","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref6","article-title":"The Art of ComputerProgramming","volume":"4a","author":"knuth","year":"0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.125"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0817-5_1"},{"key":"ref7","article-title":"Computational complexity of logic synthesis and optimization","author":"keutzer","year":"1989","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"journal-title":"Benchmarks","article-title":"IWLS","year":"2005","key":"ref2"},{"article-title":"Optimal combinational multi-level logic synthesis","year":"2009","author":"ernst","key":"ref9"},{"key":"ref1","article-title":"Logic Synthesis and Optimization Benchmarks, Version 3.0","author":"yang","year":"1991","journal-title":"Rep Microelectronics Center of North Carolina"},{"key":"ref20","first-page":"677691","article-title":"Graph-Based Algorithms for Boolean Function Manipulation","volume":"c 35","author":"randal","year":"1986","journal-title":"IEEE Transactions on Computers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105357"},{"key":"ref21","article-title":"Progressive generation of canonical sums of products using a SAT solver","author":"petkovska","year":"2016","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref24","article-title":"Boolean Logic Optimization in Majority-Inverter Graphs","author":"amaru","year":"2015","journal-title":"Design Automation Conference (DAC)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref26","article-title":"Optimizing Majority-Inverter Graphs With Functional Hashing","author":"soeken","year":"2016","journal-title":"Proc of the Conference on Design Automation and Test in Europe (DATE)"},{"key":"ref25","article-title":"Majority-Inverter Graphs: A New Paradigm for Logic Optimization","volume":"35","author":"amaru","year":"2015","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2017,1,16]]},"location":"Chiba, Japan","end":{"date-parts":[[2017,1,19]]}},"container-title":["2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7847727\/7858249\/07858313.pdf?arnumber=7858313","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T15:16:06Z","timestamp":1513178166000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7858313\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2017.7858313","relation":{},"subject":[],"published":{"date-parts":[[2017,1]]}}}