{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:27:34Z","timestamp":1725535654323},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/aspdac.2017.7858325","type":"proceedings-article","created":{"date-parts":[[2017,2,20]],"date-time":"2017-02-20T16:36:54Z","timestamp":1487608614000},"page":"232-237","source":"Crossref","is-referenced-by-count":4,"title":["Virtual prototyping of smart systems through automatic abstraction and mixed-signal scheduling"],"prefix":"10.1109","author":[{"given":"Michele","family":"Lora","sequence":"first","affiliation":[]},{"given":"Enrico","family":"Fraccaroli","sequence":"additional","affiliation":[]},{"given":"Franco","family":"Fummi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"SPICE: Simulation program with integrated circuit emphasis","author":"nagel","year":"1973","journal-title":"Electronics Research Laboratory College of Engineering University of California"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.841071"},{"key":"ref12","article-title":"Code Manipulation for Virtual Platform Integration","author":"vinco","year":"2015","journal-title":"IEEE Transactions on Computers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2015.7306361"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/530144a"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496665"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1006\/jsco.2001.0494"},{"journal-title":"Carbon Design Systems Carbon Model Studio","year":"0","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-27392-1"},{"key":"ref8","first-page":"1586","article-title":"Integration of Mixed-Signal Components into Virtual Platforms for Holistic Simulation of Smart Systems","author":"enrico fraccaroli","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004154"},{"key":"ref2","first-page":"1337","article-title":"Towards improving simulation of analog circuits using model order reduction","author":"henda","year":"2012","journal-title":"Proc ACM\/IEEE Design Automation and Test in Europe (DATE)"},{"journal-title":"Verilog-A Language Reference Manual","year":"0","key":"ref1"},{"journal-title":"OVP Open Virtual Platform","year":"0","key":"ref9"}],"event":{"name":"2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2017,1,16]]},"location":"Chiba, Japan","end":{"date-parts":[[2017,1,19]]}},"container-title":["2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7847727\/7858249\/07858325.pdf?arnumber=7858325","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,9]],"date-time":"2017-03-09T08:28:30Z","timestamp":1489048110000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7858325\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2017.7858325","relation":{},"subject":[],"published":{"date-parts":[[2017,1]]}}}