{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:14:55Z","timestamp":1780636495345,"version":"3.54.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/aspdac.2017.7858368","type":"proceedings-article","created":{"date-parts":[[2017,2,20]],"date-time":"2017-02-20T16:36:54Z","timestamp":1487608614000},"page":"475-480","source":"Crossref","is-referenced-by-count":34,"title":["Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits"],"prefix":"10.1109","author":[{"given":"Tuotian","family":"Liao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lihong","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2013.2281535"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2015.2420112"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.905671"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2334492"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364569"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917594"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271714"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.854608"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.04.005"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2014.07.002"},{"key":"ref8","first-page":"17","article-title":"Analog integrated circuit sizing and layout dependent effects: A review","volume":"3","author":"liao","year":"2014","journal-title":"Solid State Electronics Microelectronic Journal"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.09.003"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158732"},{"key":"ref1","first-page":"145","article-title":"Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits","author":"agarwal","year":"2004","journal-title":"Proc Design Automation Conf (DAC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2007.892759"}],"event":{"name":"2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Chiba, Japan","start":{"date-parts":[[2017,1,16]]},"end":{"date-parts":[[2017,1,19]]}},"container-title":["2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7847727\/7858249\/07858368.pdf?arnumber=7858368","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,9]],"date-time":"2017-03-09T08:13:29Z","timestamp":1489047209000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7858368\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2017.7858368","relation":{},"subject":[],"published":{"date-parts":[[2017,1]]}}}