{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:48:51Z","timestamp":1730198931840,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/aspdac.2017.7858381","type":"proceedings-article","created":{"date-parts":[[2017,2,20]],"date-time":"2017-02-20T16:36:54Z","timestamp":1487608614000},"page":"549-553","source":"Crossref","is-referenced-by-count":1,"title":["Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization"],"prefix":"10.1109","author":[{"given":"Wei-Hsun","family":"Liao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang-Tzu","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sheng-Hsin","family":"Fang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chien-Chia","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ding-Ming","family":"Kwai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Fa","family":"Chou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419899"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974687"},{"year":"0","key":"ref10","article-title":"EPS 3.1"},{"key":"ref6","first-page":"1","article-title":"3-D Centric Technology and Realization with TSV","author":"lin","year":"2012","journal-title":"International Symposium on VLSI Design Automation and Test (VLSI-DAT)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118405"},{"key":"ref5","first-page":"509","article-title":"HS3DPG: Hierarchical Simulation for 3D P\/G Network","author":"tao","year":"2013","journal-title":"Proceedings of the Asia and South Pacific Design Automation Conference"},{"year":"0","key":"ref12","article-title":"IBM ILOG CPLEX Optimizer"},{"year":"0","key":"ref8","article-title":"Lef\/Def Exchange Format"},{"key":"ref7","first-page":"1","article-title":"Three-Dimensional and 2.5d Dimensional Interconnection Technology: State of the Art","volume":"136","author":"liu","year":"2014","journal-title":"Electronic Packaging"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.343"},{"year":"0","key":"ref9","article-title":"EDI 14.14"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337616"}],"event":{"name":"2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2017,1,16]]},"location":"Chiba, Japan","end":{"date-parts":[[2017,1,19]]}},"container-title":["2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7847727\/7858249\/07858381.pdf?arnumber=7858381","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,9]],"date-time":"2017-03-09T08:22:22Z","timestamp":1489047742000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7858381\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2017.7858381","relation":{},"subject":[],"published":{"date-parts":[[2017,1]]}}}