{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:13:12Z","timestamp":1767262392792},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/aspdac.2018.8297299","type":"proceedings-article","created":{"date-parts":[[2018,2,22]],"date-time":"2018-02-22T17:02:02Z","timestamp":1519318922000},"page":"159-165","source":"Crossref","is-referenced-by-count":2,"title":["MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits"],"prefix":"10.1109","author":[{"given":"Yutaka","family":"Masuda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masanori","family":"Hashimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967019"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2015.7342404"},{"key":"ref12","first-page":"81","article-title":"Con-trolled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI","author":"teman","year":"2015","journal-title":"Proc ASP-DAC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2016.7833424"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2281986"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2014.6948799"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850834"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996663"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2015.2506605"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.23"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338418"},{"key":"ref2","first-page":"1","article-title":"On the simulation of NBTI-Induced performance degradation considering arbitrary temperature and voltage variations","author":"wang","year":"2014","journal-title":"Proc DAC"},{"key":"ref1","first-page":"774","article-title":"Modeling of nbti-induced pmos degradation under arbitrary dynamic temperature variation","author":"zang","year":"2008","journal-title":"Proc ISQED"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2101089"}],"event":{"name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","start":{"date-parts":[[2018,1,22]]},"location":"Jeju","end":{"date-parts":[[2018,1,25]]}},"container-title":["2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8291862\/8297256\/08297299.pdf?arnumber=8297299","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,11]],"date-time":"2018-04-11T17:11:46Z","timestamp":1523466706000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8297299\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2018.8297299","relation":{},"subject":[],"published":{"date-parts":[[2018,1]]}}}