{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:57:04Z","timestamp":1780444624099,"version":"3.54.1"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/aspdac.2018.8297375","type":"proceedings-article","created":{"date-parts":[[2018,2,22]],"date-time":"2018-02-22T17:02:02Z","timestamp":1519318922000},"page":"513-520","source":"Crossref","is-referenced-by-count":21,"title":["Optimal die placement for interposer-based 3D ICs"],"prefix":"10.1109","author":[{"given":"Sergii","family":"Osmolovskyi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Johann","family":"Knechtel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Igor L.","family":"Markov","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jens","family":"Lienig","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248841"},{"key":"ref11","first-page":"1","article-title":"AMD's next generation GPU and high bandwidth memory architecture: FURY","author":"macri","year":"2015","journal-title":"Hot Chips Symp"},{"key":"ref12","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency","author":"dorsey","year":"2010","journal-title":"Tech Rep"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2014.6897596"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488767"},{"key":"ref15","first-page":"524","article-title":"Automatic die placement and flexible I\/O assignment in 2. 5D IC design","author":"seemuth","year":"2015","journal-title":"Proc IEEE Int Symp Quality Electron Des"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593142"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1002\/ecjc.4430760702"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.07.001"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10479-008-0463-6"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830808"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1115\/IPACK2011-52189"},{"key":"ref6","first-page":"56: 1","article-title":"Cost analysis and cost-driven IP reuse methodology for SoC design based on 2. 5D\/3D integration","author":"stow","year":"2016","journal-title":"Proc Int Conf Comp -Aided Des"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131506"},{"key":"ref8","first-page":"1","article-title":"Physical Design Challenges and Solutions for Interposer-Based 3D Systems","author":"osmolovskyi","year":"2017","journal-title":"Design Reliability"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2666604"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref1","article-title":"Lithography-induced limits to scaling of design quality","volume":"9053","author":"kahng","year":"2014","journal-title":"Proc SPIE Adv Lithography"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.10.45"},{"key":"ref20","author":"osmolovskyi","year":"2017","journal-title":"Placement framework for interposer-based 3D ICs"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858266"}],"event":{"name":"2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)","location":"Jeju","start":{"date-parts":[[2018,1,22]]},"end":{"date-parts":[[2018,1,25]]}},"container-title":["2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8291862\/8297256\/08297375.pdf?arnumber=8297375","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,11]],"date-time":"2018-04-11T17:11:12Z","timestamp":1523466672000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8297375\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/aspdac.2018.8297375","relation":{},"subject":[],"published":{"date-parts":[[2018,1]]}}}