{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T14:25:41Z","timestamp":1725546341164},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/asscc.2014.7008871","type":"proceedings-article","created":{"date-parts":[[2015,1,19]],"date-time":"2015-01-19T21:48:18Z","timestamp":1421704098000},"page":"105-108","source":"Crossref","is-referenced-by-count":0,"title":["A 23mW\/lane 1.2–6.8Gb\/s multi-standard transceiver in 28nm CMOS"],"prefix":"10.1109","author":[{"given":"Seong-Ho","family":"Lee","sequence":"first","affiliation":[]},{"given":"Duke","family":"Tran","sequence":"additional","affiliation":[]},{"given":"Tamer","family":"Ali","sequence":"additional","affiliation":[]},{"given":"Burak","family":"Catli","sequence":"additional","affiliation":[]},{"given":"Heng","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Mohammed","family":"Abdul-Latif","sequence":"additional","affiliation":[]},{"given":"Zhi","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Guansheng","family":"Li","sequence":"additional","affiliation":[]},{"given":"Mahmoud Reza","family":"Ahmadi","sequence":"additional","affiliation":[]},{"given":"Afshin","family":"Momtaz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274824"},{"key":"2","first-page":"177","article-title":"A 5Gb\/s low-power pci express\/usb3.0 ready phy in 40nm cmos technology with high-jitter immunity","author":"lin","year":"2009","journal-title":"Proc IEEE Asian Solid State Circuits Conf"},{"key":"1","first-page":"37","article-title":"An ASIC-ready 1.25-6.25 Gb\/s SerDes in 90 nm CMOS with multi-standard compatibility","author":"nishi","year":"2008","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"7","first-page":"160c","article-title":"A 288fs rms jitter versatile 8-12.4ghz wide-band fractional-n synthesizer for sonet and serdes communication standards in 40nm cmos","author":"ahmadi","year":"2013","journal-title":"Symposium on VLSI Circuits (VLSIC)"},{"key":"6","article-title":"A 2.8mw\/gb\/s quad-channel 8.5-11.4gb\/s quasi-digital transceiver in 28nm cmos","author":"nazemi","year":"0","journal-title":"IEEE VLSI Symposium 2013"},{"key":"5","first-page":"1","article-title":"A 10 Gb\/s 10 mW 2-Tap reconfigurable pre-emphasis transmitter in 65 nm LP CMOS","author":"lu","year":"2012","journal-title":"Proc IEEE Custom Integrated Circuits Conf"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617598"}],"event":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2014,11,10]]},"location":"KaoHsiung, Taiwan","end":{"date-parts":[[2014,11,12]]}},"container-title":["2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6996072\/7008838\/07008871.pdf?arnumber=7008871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:34:00Z","timestamp":1490304840000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7008871\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/asscc.2014.7008871","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}