{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T12:15:30Z","timestamp":1771330530117,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/asscc.2014.7008879","type":"proceedings-article","created":{"date-parts":[[2015,1,20]],"date-time":"2015-01-20T02:48:18Z","timestamp":1421722098000},"page":"137-140","source":"Crossref","is-referenced-by-count":12,"title":["A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory"],"prefix":"10.1109","author":[{"given":"Aravinthan","family":"Athmanathan","sequence":"first","affiliation":[]},{"given":"Milos","family":"Stanisavljevic","sequence":"additional","affiliation":[]},{"given":"Junho","family":"Cheon","sequence":"additional","affiliation":[]},{"given":"Seokjoon","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Changyong","family":"Ahn","sequence":"additional","affiliation":[]},{"given":"Junghyuk","family":"Yoon","sequence":"additional","affiliation":[]},{"given":"Minchul","family":"Shin","sequence":"additional","affiliation":[]},{"given":"Taekseung","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Nikolaos","family":"Papandreou","sequence":"additional","affiliation":[]},{"given":"Haris","family":"Pozidis","sequence":"additional","affiliation":[]},{"given":"Evangelos","family":"Eleftheriou","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873231"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1116\/1.3301579"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/4.597284"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1063\/1.328036"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703445"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2016397"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1063\/1.3653279"},{"key":"9","doi-asserted-by":"crossref","first-page":"1521","DOI":"10.1109\/TCSI.2012.2220459","article-title":"A 256-mcell phasechange memory chip operating at 2+ bit\/cell","volume":"60","author":"close","year":"2013","journal-title":"IEEE Trans Circuits and Systems I Regular Papers"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131482"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSP.2013.6622745"}],"event":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"KaoHsiung, Taiwan","start":{"date-parts":[[2014,11,10]]},"end":{"date-parts":[[2014,11,12]]}},"container-title":["2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6996072\/7008838\/07008879.pdf?arnumber=7008879","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:55:03Z","timestamp":1498190103000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7008879\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/asscc.2014.7008879","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}