{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:05:27Z","timestamp":1729670727300,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/asscc.2014.7008935","type":"proceedings-article","created":{"date-parts":[[2015,1,20]],"date-time":"2015-01-20T02:48:18Z","timestamp":1421722098000},"page":"361-364","source":"Crossref","is-referenced-by-count":0,"title":["A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2<\/sup> all-digital delay-locked loop in 65-nm CMOS"],"prefix":"10.1109","author":[{"given":"Chun-Yuan","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Jinn-Shyan","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Pei-Yuan","family":"Chou","sequence":"additional","affiliation":[]},{"given":"Shiou-Ching","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chi-Tien","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Yuan-Hua","family":"Chu","sequence":"additional","affiliation":[]},{"given":"Tzu-Yi","family":"Yang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977308"},{"key":"2","first-page":"282","article-title":"A 0.1-to-1.5GHz 4.2mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology","author":"yun","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"1","first-page":"156","article-title":"A sub-100?W multi-functional cardiac signal processor for mobile healthcare applications","author":"hsu","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"7","doi-asserted-by":"crossref","first-page":"2338","DOI":"10.1109\/JSSC.2007.906183","article-title":"A 2.5 GHz all-digital delay-locked loop in 0.13?m CMOS technology","volume":"42","author":"yang","year":"2007","journal-title":"IEEE J Solid-State Circuits"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243852"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176994"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.843596"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2049387"}],"event":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2014,11,10]]},"location":"KaoHsiung, Taiwan","end":{"date-parts":[[2014,11,12]]}},"container-title":["2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6996072\/7008838\/07008935.pdf?arnumber=7008935","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:55:03Z","timestamp":1498190103000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7008935\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/asscc.2014.7008935","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}