{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,25]],"date-time":"2026-01-25T05:04:18Z","timestamp":1769317458512,"version":"3.49.0"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/asscc.2015.7387432","type":"proceedings-article","created":{"date-parts":[[2016,1,21]],"date-time":"2016-01-21T23:12:35Z","timestamp":1453417955000},"page":"1-4","source":"Crossref","is-referenced-by-count":17,"title":["A cell current compensation scheme for 3D NAND FLASH memory"],"prefix":"10.1109","author":[{"given":"SungWook","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"KyuTae","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Passerini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"HeeJoung","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"DoYoung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"ChiHyun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"KunWoo","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"JinWoong","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Modeling and characterization of program\/erasure speedand retention of TiN-gate MANOS cells for NAND flash memory","author":"choi","year":"0"},{"key":"ref3","first-page":"327","article-title":"A novel NAND-type MONOS memory using 64nmprocess technology for multi-gigabit flash EEPROMs","author":"shin","year":"2005","journal-title":"IEEE International Electron Devices Meeting"},{"key":"ref5","first-page":"92","article-title":"Chip level reliability of MANOS cells under operationconditions","author":"choi","year":"2009","journal-title":"IEEE International Memory Workshop"},{"key":"ref2","article-title":"Bit cost scalable technology with punch and plug process","author":"tanaka","year":"0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873207"}],"event":{"name":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"Xia'men, China","start":{"date-parts":[[2015,11,9]]},"end":{"date-parts":[[2015,11,11]]}},"container-title":["2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7378179\/7387429\/07387432.pdf?arnumber=7387432","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T03:19:07Z","timestamp":1490411947000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7387432\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/asscc.2015.7387432","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}