{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T15:49:33Z","timestamp":1764172173590,"version":"3.44.0"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/asscc.2015.7387434","type":"proceedings-article","created":{"date-parts":[[2016,1,21]],"date-time":"2016-01-21T18:12:35Z","timestamp":1453399955000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["A 1.74mW\/GHz 0.11\u20132.5GHz fast-locking, jitter-reducing, 180\u00b0 phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers"],"prefix":"10.1109","author":[{"given":"Joo-Hyung","family":"Chae","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Gi-Moon","family":"Hong","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Jihwan","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Mino","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Hyeongjun","family":"Ko","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Woo-Yeol","family":"Shin","sequence":"additional","affiliation":[{"name":"SK hynix, Icheon, Korea"}]},{"given":"Hankyu","family":"Chi","sequence":"additional","affiliation":[{"name":"SK hynix, Icheon, Korea"}]},{"given":"Deog-Kyoon","family":"Jeong","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]},{"given":"Suhwan","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542310"},{"key":"ref3","first-page":"158","article-title":"A 1.3mW, 1.6GHz digital delay-locked loop with two-cycle locking time and dither-free tracking","author":"kim","year":"2013","journal-title":"IEEE Symp on VLSI Circuits"},{"key":"ref10","first-page":"341","article-title":"A 0.1&#x2013;1.5GHz all-digital phase inversion delay-locked loop","author":"han","year":"2013","journal-title":"IEEE Asian Solid-State Circuits Conf"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2313131"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658534"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658530"},{"key":"ref12","first-page":"82","article-title":"A 0.17&#x2013;1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme","author":"shin","year":"2008","journal-title":"IEEE European Solid-State Circuits Conf"},{"key":"ref8","first-page":"244","article-title":"A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS","author":"hsieh","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2048379"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016993"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858375"},{"key":"ref1","first-page":"244","article-title":"A 400MHz-1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface","author":"hossain","year":"2013","journal-title":"IEEE Symp on VLSI Circuits"}],"event":{"name":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2015,11,9]]},"location":"Xiamen, China","end":{"date-parts":[[2015,11,11]]}},"container-title":["2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7378179\/7387429\/07387434.pdf?arnumber=7387434","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:28:44Z","timestamp":1755908924000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7387434\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/asscc.2015.7387434","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}