{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:52:20Z","timestamp":1729615940548,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/asscc.2015.7387450","type":"proceedings-article","created":{"date-parts":[[2016,1,21]],"date-time":"2016-01-21T23:12:35Z","timestamp":1453417955000},"page":"1-4","source":"Crossref","is-referenced-by-count":4,"title":["A digital bang-bang phase-locked loop with bandwidth calibration"],"prefix":"10.1109","author":[{"given":"Chi-Huan","family":"Chiang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang-Cheng","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shen-Iuan","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"248","article-title":"A 0.022mm2 970? W dual-loop injection-locked PLL with ?243dB FOM using synthesizable all-digital PVT calibration circuits","author":"deng","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","first-page":"250","article-title":"A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range","author":"kim","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2268640"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176995"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"key":"ref2","first-page":"266","article-title":"A 0.0066mm2 780?W fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique","author":"deng","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757430"}],"event":{"name":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2015,11,9]]},"location":"Xia'men, China","end":{"date-parts":[[2015,11,11]]}},"container-title":["2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7378179\/7387429\/07387450.pdf?arnumber=7387450","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T04:14:48Z","timestamp":1498277688000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7387450\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/asscc.2015.7387450","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}