{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T10:36:30Z","timestamp":1725705390435},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/asscc.2016.7844162","type":"proceedings-article","created":{"date-parts":[[2017,2,10]],"date-time":"2017-02-10T15:58:46Z","timestamp":1486742326000},"page":"169-172","source":"Crossref","is-referenced-by-count":3,"title":["Design of non-contact 2Gb\/s I\/O test methods for high bandwidth memory (HBM)"],"prefix":"10.1109","author":[{"given":"Hyunui","family":"Lee","sequence":"first","affiliation":[]},{"given":"Sukyong","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Hye-Seung","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Won-Joo","family":"Yun","sequence":"additional","affiliation":[]},{"given":"Jae-Hun","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Sungoh","family":"Ahn","sequence":"additional","affiliation":[]},{"given":"Wang-Soo","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Beomyong","family":"Kil","sequence":"additional","affiliation":[]},{"given":"Yoo-Chang","family":"Sung","sequence":"additional","affiliation":[]},{"given":"Sang-Hoon","family":"Shin","sequence":"additional","affiliation":[]},{"given":"Yong-Sik","family":"Park","sequence":"additional","affiliation":[]},{"given":"Yong-Hwan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Kyung-Woo","family":"Nam","sequence":"additional","affiliation":[]},{"given":"Indal","family":"Song","sequence":"additional","affiliation":[]},{"given":"Kyomin","family":"Sohn","sequence":"additional","affiliation":[]},{"given":"Yong-Cheol","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Jung-Hwan","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Seong-Jin","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Gyo-Young","family":"Jin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"605","article-title":"Loopback Architecture for Wafer-Level At-Speed Testing of Embedded Hyper Transport Processor Links","author":"loke","year":"2009","journal-title":"IEEE Custom Integrated Circuits Conference (CICC)"},{"key":"ref3","first-page":"23","article-title":"AC IO loopback design for high speed &#x00B5;processor IO test","author":"provost","year":"2004","journal-title":"International Test Conference (ITC)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2360379"},{"key":"ref1","first-page":"498","article-title":"A 40nm 2Gb 7Gb\/s\/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW","author":"bae","year":"2011","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2016,11,7]]},"location":"Toyama, Japan","end":{"date-parts":[[2016,11,9]]}},"container-title":["2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7833314\/7844119\/07844162.pdf?arnumber=7844162","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T22:50:14Z","timestamp":1488408614000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7844162\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/asscc.2016.7844162","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}