{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,10]],"date-time":"2026-05-10T03:08:11Z","timestamp":1778382491893,"version":"3.51.4"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/asscc.2017.8240204","type":"proceedings-article","created":{"date-parts":[[2017,12,28]],"date-time":"2017-12-28T16:32:34Z","timestamp":1514478754000},"page":"13-16","source":"Crossref","is-referenced-by-count":5,"title":["A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same\/different row access mode"],"prefix":"10.1109","author":[{"given":"Yoshisato","family":"Yokoyama","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuichiro","family":"Ishii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haruyuki","family":"Okuda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"Nii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586011"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716538"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164021"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858411"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2014.7008851"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573459"},{"key":"ref16","first-page":"17","article-title":"A 5.92-Mb\/mm2 28-nm Pseudo 2-Read\/Write Dualport SRAM using Double Pumping Circuitry","author":"ishii","year":"2016","journal-title":"Proc A-SSCC"},{"key":"ref4","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.093"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.3.91"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718338"},{"key":"ref8","first-page":"508","article-title":"A 90 nm dual-port SRAM with 2.04 ?m2 8T-thin cell using dynamically-controlled column bias scheme","volume":"543","author":"nii","year":"2004","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref7","year":"2003","journal-title":"US Patent"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342724"},{"key":"ref1","first-page":"194","volume":"593","author":"shiota","year":"2005","journal-title":"ISSCC Digest"},{"key":"ref9","first-page":"130","article-title":"A 65 nm Ultra-High-DensityDual-Port SRAM with 0.71?m2 8T-Cell for SoC","author":"nii","year":"2006","journal-title":"VLSI Circuits Symp Dig"}],"event":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"Seoul","start":{"date-parts":[[2017,11,6]]},"end":{"date-parts":[[2017,11,8]]}},"container-title":["2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8226344\/8240197\/08240204.pdf?arnumber=8240204","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T17:34:41Z","timestamp":1517852081000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8240204\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/asscc.2017.8240204","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}