{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,14]],"date-time":"2026-01-14T04:15:37Z","timestamp":1768364137772,"version":"3.49.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/asscc.2018.8579314","type":"proceedings-article","created":{"date-parts":[[2019,1,8]],"date-time":"2019-01-08T17:59:07Z","timestamp":1546970347000},"page":"5-8","source":"Crossref","is-referenced-by-count":11,"title":["A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS"],"prefix":"10.1109","author":[{"given":"Shenggao","family":"Li","sequence":"first","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Fulvio","family":"Spagna","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Ji","family":"Chen","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Xiaoqing","family":"Wang","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Luke","family":"Tong","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Sujatha","family":"Gowder","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Wenyan","family":"Jia","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Roan","family":"Nicholson","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Sita","family":"Iyer","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Rui","family":"Song","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Lily","family":"Li","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Meng-hung","family":"Chen","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Amanda","family":"Tran","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Michael De","family":"Vita","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Deepar","family":"Govindrajan","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Marcus","family":"Pasquarella","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Dave","family":"Bradley","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Frank","family":"Verdico","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Matt","family":"Duwe","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Eric","family":"Lee","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]},{"given":"Michelle","family":"Wigton","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, United States"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093326"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2344008"},{"key":"ref6","article-title":"A 3.8mW\/Gbps Quad-Channel 8.5-13Gbps Serial Link With a 5 Tap DFE and 4 tap Transmit FFE in 28nm CMOS","author":"kocaman","year":"2016","journal-title":"JSSC"},{"key":"ref5","article-title":"A 28Gb\/s Multistandar Serial Link Transceiver for Backplane Applications in 28nm CMOS","author":"zhang","year":"2015","journal-title":"JSSC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487622"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573472"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196313"},{"key":"ref9","year":"0","journal-title":"PCIe 4 0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2702711"}],"event":{"name":"2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)","location":"Tainan, Taiwan","start":{"date-parts":[[2018,11,5]]},"end":{"date-parts":[[2018,11,7]]}},"container-title":["2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8547238\/8579249\/08579314.pdf?arnumber=8579314","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T20:57:22Z","timestamp":1768337842000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8579314\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/asscc.2018.8579314","relation":{},"subject":[],"published":{"date-parts":[[2018,11]]}}}