{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:49:11Z","timestamp":1729640951572,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/async.2004.1299283","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"7-16","source":"Crossref","is-referenced-by-count":1,"title":["A fast and energy-ef .cient stack"],"prefix":"10.1109","author":[{"given":"J.","family":"Ebergen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Finchelstein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Kao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Lexau","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Hopkins","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"An asynchronous stack with constant response time","volume":"cs 93 11","author":"ebergen","year":"1993","journal-title":"Technical Report"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1109\/ASYNC.2004.1299287","article-title":"Transistor sizing with logical effort: How to control the speed and energy consumption of a circuit","author":"ebergen","year":"2004","journal-title":"Proc International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/ASYNC.2001.914083"},{"key":"7","first-page":"387","article-title":"A low-power, high-speed stack controller designed using asynchronous circuit techniques","author":"pessolano","year":"1998","journal-title":"Power and Timing Modeling Optimization and Simulation"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/5.740022"},{"key":"5","first-page":"224","article-title":"A synthesis method for self-timed VLSI circuits","author":"martin","year":"1987","journal-title":"Proc International Conf Computer Design (ICCD)"},{"key":"4","first-page":"123","article-title":"Implementing a stack as a delay-insensitive circuit","volume":"a 28","author":"josephs","year":"1993","journal-title":"Asynchronous Design Methodologies Volume A-28 of IFIP Transactions"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ASYNC.2001.914082"}],"event":{"name":"10th International Symposium on Asynchronous Circuits and Systems, 2004.","location":"Crete, Greece"},"container-title":["10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9094\/28866\/01299283.pdf?arnumber=1299283","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T07:57:23Z","timestamp":1497599843000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1299283\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/async.2004.1299283","relation":{},"subject":[]}}